利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

42 records (took 0.023 seconds)

    Current-mode sense amplifier and reference current circuitry
    5.
    发明授权
    Current-mode sense amplifier and reference current circuitry 有权
    电流模式读出放大器和参考电流电路

    公开(公告)号：US09564188B2

    公开(公告)日：2017-02-07

    申请号：US14840367

    申请日：2015-08-31

    Applicant: International Business Machines Corporation

    Inventor： Alexander Fritsch ,  Gerhard Hellner ,  Michael Kugel ,  Rolf Sautter

    IPC: G11C7/02 ,  G11C7/14 ,  G11C7/06

    CPC classification number: G11C7/14 ,  G11C5/147 ,  G11C7/065

    Abstract: An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal. The amplifier is further configured to generate a second logical value at the first output terminal of the amplifier in response to the sense current being higher than the reference current.

    Abstract translation: 电子电路包括电流检测放大器。 放大器包括参考电流输入端子，感测电流输入端子和第一输出端子。 电子电路包括参考电流源。 参考电流源包括串联连接的两个参考n-FET堆叠，参考电流输入端子通过两个参考n-FET堆叠耦合到接地端子。 电子电路包括多个存储单元，每个存储单元通过相应的感测n-FET堆并联耦合到感测电流输入端。 放大器被配置为响应于感测电流输入端子的感测电流低于参考电流输入端子的参考电流，在放大器的第一输出端产生第一逻辑值。 放大器还被配置为响应于感测电流高于参考电流而在放大器的第一输出端产生第二逻辑值。

    Testing content addressable memory and random access memory
    6.
    发明授权
    Testing content addressable memory and random access memory 有权

    公开(公告)号：US10593420B2

    公开(公告)日：2020-03-17

    申请号：US15898861

    申请日：2018-02-19

    Applicant: International Business Machines Corporation

    Inventor： Harry Barowski ,  Sheldon Levenstein ,  Pradip Patel ,  Daniel Rodko ,  Gordon B. Sapp ,  Rolf Sautter

    IPC: G11C29/40 ,  G11C29/44 ,  G11C15/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/36

    Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.

    Structure for reducing pre-charge voltage for static random-access memory arrays
    10.
    发明授权
    Structure for reducing pre-charge voltage for static random-access memory arrays 有权
    用于降低静态随机存取存储器阵列的预充电电压的结构

    公开(公告)号：US09431098B1

    公开(公告)日：2016-08-30

    申请号：US14822089

    申请日：2015-08-10

    Applicant: International Business Machines Corporation

    Inventor： Alexander Fritsch ,  Amira Rozenfeld ,  Rolf Sautter ,  Dieter Wendel

    IPC: G11C5/06 ,  G11C11/419

    CPC classification number: G11C11/416 ,  G06F17/5045 ,  G06F17/5081 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C11/418 ,  G11C11/419 ,  H01L23/528 ,  H01L27/1104

    Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

    Abstract translation: 可以提供SRAM单元组的存储单元布置，其中在每个组中，多个SRAM单元通过至少一个公共局部位线连接到本地读取放大器的输入。 放大器的输出连接到共享的全局位线。 全局位线连接到预充电电路，并且预充电电路适于在读取数据之前用可编程预充电电压对全局位线进行预充电。 预充电电路包括限幅器电路，其包括连接到全局位线的预充电调节器电路，以用可编程预充电电压对全局位线预充电;以及评估和转换电路，连接到 预充电调节器电路和全局位线，以补偿全局位线的泄漏电流，而不改变其电压电平。

Patent Agency Ranking