公开(公告)号：US20170308454A1

公开(公告)日：2017-10-26

申请号：US15138593

申请日：2016-04-26

Applicant: International Business Machines Corporation

Inventor： Khandker N. ADEEB ,  Steven J. BATTLE ,  Brandon R. GODDARD ,  Dung Q. NGUYEN ,  Tu-An T. NGUYEN ,  Nicholas R. ORZOL ,  Brian D. VICTOR ,  Brendan M. WONG

IPC: G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3495 ,  G01R31/31705 ,  G06F11/3024

Abstract: Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.

公开(公告)号：US20190187993A1

公开(公告)日：2019-06-20

申请号：US15845871

申请日：2017-12-18

Applicant: International Business Machines Corporation

Inventor： Kenneth L. WARD ,  Susan E. EISEN ,  Dung Q. NGUYEN ,  Glenn O. KINCAID ,  Christopher M. MUELLER ,  Tu-An T. NGUYEN ,  Gaurav MITTAL ,  Deepak K. SINGH

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30145

Abstract: A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.

公开(公告)号：US20180336108A1

公开(公告)日：2018-11-22

申请号：US15596818

申请日：2017-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steven J. BATTLE ,  Joshua W. BOWMAN ,  Sundeep CHADHA ,  Dhivya JEGANATHAN ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN ,  Tu-An T. NGUYEN ,  David R. TERRY

IPC: G06F11/16 ,  G06F11/20 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments include systems, methods, and computer program products for on-demand error detection and correction of registers in a processor. One method includes detecting, before a first instruction is dispatched to an issue queue in the processor, an error in data, associated with the first instruction, stored in an entry of a register file in the processor. The method also includes, after detecting the error, halting the dispatch of the first instruction to the issue queue, and determining whether the entry of the register file has completed. The method further includes determining whether to perform error correction on the register file based on the determination of whether the entry of the register file has completed.