公开(公告)号：US20170003969A1

公开(公告)日：2017-01-05

申请号：US14755570

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Salma AYUB ,  Josh BOWMAN ,  Sundeep CHADHA ,  Dhivya JEGANATHAN ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F1/10 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851

Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.

公开(公告)号：US20170003971A1

公开(公告)日：2017-01-05

申请号：US15072670

申请日：2016-03-17

Applicant: International Business Machines Corporation

Inventor： Salma Ayub ,  Josh BOWMAN ,  Sundeep CHADHA ,  Dhivya JEGANATHAN ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN

IPC: G06F9/38 ,  G06F1/10 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F1/10 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851

Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.

Abstract translation: 本文公开的技术描述了用于在处理器中交织指令标签的可变等待时间管线。 根据本文提出的一个实施例，指令标签与从发布队列发出指令的指令相关联。 确定延迟管中的多个位置之一。 管道存储一个或多个指令标签，每个指令标签与相应的指令相关联。 管道还基于每个相应指令的等待时间将指令标签存储在相应的位置。 指令标签存储在管道中确定的位置。

公开(公告)号：US20180336108A1

公开(公告)日：2018-11-22

申请号：US15596818

申请日：2017-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steven J. BATTLE ,  Joshua W. BOWMAN ,  Sundeep CHADHA ,  Dhivya JEGANATHAN ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN ,  Tu-An T. NGUYEN ,  David R. TERRY

IPC: G06F11/16 ,  G06F11/20 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments include systems, methods, and computer program products for on-demand error detection and correction of registers in a processor. One method includes detecting, before a first instruction is dispatched to an issue queue in the processor, an error in data, associated with the first instruction, stored in an entry of a register file in the processor. The method also includes, after detecting the error, halting the dispatch of the first instruction to the issue queue, and determining whether the entry of the register file has completed. The method further includes determining whether to perform error correction on the register file based on the determination of whether the entry of the register file has completed.

公开(公告)号：US20170168818A1

公开(公告)日：2017-06-15

申请号：US15044412

申请日：2016-02-16

Applicant: International Business Machines Corporation

Inventor： Salma AYUB ,  Brian D. BARRICK ,  Joshua W. BOWMAN ,  Sundeep CHADHA ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN ,  David R. TERRY ,  Jing ZHANG

IPC: G06F9/30

CPC classification number: G06F9/3012 ,  G06F9/30043 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3891

Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.

公开(公告)号：US20170109167A1

公开(公告)日：2017-04-20

申请号：US14883301

申请日：2015-10-14

Applicant: International Business Machines Corporation

Inventor： Susan E. EISEN ,  Cliff KUCHARSKI ,  Hung Q. LE ,  Dung Q. NGUYEN ,  David R. TERRY

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30072 ,  G06F9/30 ,  G06F9/30098 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/60

Abstract: Method and system for restoring data to a register file of a processing unit are provided. A history buffer entry (HBE) is marked for restoration to a register file entry. Result data and control information is sent from the HBE to an Issue Queue (ISQ). The ISQ issues an instruction for loading the result data into the register file entry based on the control information. A write back operation is performed to restore the result data to the register file entry, in response to issuing of the instruction.

公开(公告)号：US20170109171A1

公开(公告)日：2017-04-20

申请号：US14883349

申请日：2015-10-14

Applicant: International Business Machines Corporation

Inventor： Susan E. EISEN ,  Cliff KUCHARSKI ,  Hung Q. LE ,  Dung Q. NGUYEN ,  David R. TERRY

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30098 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/60

Abstract: Method and system for writing a history buffer in a processing unit is provided. At least a first instruction and a second instruction are dispatched in a single processing cycle, targeting a same register file entry. The processing unit includes two or more processing slices, each processing slice comprising a corresponding history buffer and at least a portion of a register file. Upon determining that first result data corresponding to the first instruction is older than second result data corresponding to the second instruction, the first result data is written into a history buffer bypassing the register file entry, in response to the determination. Further, the second result data is written into the register file entry.

公开(公告)号：US20170109168A1

公开(公告)日：2017-04-20

申请号：US14883420

申请日：2015-10-14

Applicant: International Business Machines Corporation

Inventor： Salma AYUB ,  Susan E. EISEN ,  Glenn O. KINCAID ,  Cliff KUCHARSKI ,  Christopher M. MUELLER ,  Dung Q. NGUYEN ,  David R. TERRY

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30098 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/604

Abstract: Method and system for managing a speculative transaction in a processing unit is provided. The speculative transaction is initiated by dispatching a first instruction indicating start of the speculative transaction. One or more register file (RF) entries are marked as pre-transaction memory (PTM), in response to the initiating. At least one second instruction targeting at least one of the marked RF entries is dispatched, while the transaction is active, wherein the at least one second instruction writes new result data into the at least one RF entry. Previous result data evicted from the at least one RF entry by the new result data, is saved into a history buffer (HB) entry. The HB entry is marked as PTM, in response to the saving, wherein the processing unit, upon detecting a trigger, is rolled back to a state before the initiating the transaction by restoring the previous result data to the at least one RF entry.

公开(公告)号：US20170109166A1

公开(公告)日：2017-04-20

申请号：US14883253

申请日：2015-10-14

Applicant: International Business Machines Corporation

Inventor： Susan E. EISEN ,  Cliff KUCHARSKI ,  Hung Q. LE ,  Dung Q. NGUYEN ,  David R. TERRY

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30072 ,  G06F9/30 ,  G06F9/30098 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/452

Abstract: Method and system for restoring results to a register file of a processing unit is provided. An instruction is dispatched in a processing slice of the processing unit, targeting a register file, wherein the processing unit includes two or more processing slices, each processing slice including a corresponding history buffer and at least a portion of a register file. The processing unit evicts previous result data from the register file entry to a history buffer corresponding to the processing slice, by writing new result data into the register file entry, in response to the instruction. The processing unit detects a trigger condition relating to a rollback of the processing unit to a previous state, and restores the previous result data from the history buffer to the register file entry, in response to the trigger.