公开(公告)号：US20170155339A1

公开(公告)日：2017-06-01

申请号：US14955037

申请日：2015-11-30

申请人： IXYS Corporation

发明人： Anatoliy V. Tsyrganovich ,  Leonid A. Neyman

IPC分类号： H02M7/219

CPC分类号： H02M7/219 ,  H02M2007/2195 ,  Y02B70/1408

摘要： A rectifier includes a larger Field Effect Transistor (FET1) and a smaller FET (FET2). A sense resistor is in series with FET2's body diode between a cathode terminal and an anode terminal. If the cathode terminal voltage is greater than the voltage on the anode terminal, then body diodes of FETs are reverse biased, the FETs are controlled to be off, and there is no current flow through the rectifier. If, however, the voltage on the anode terminal becomes positive with respect to the cathode terminal, then the body diode of FET2 starts to conduct and there is a voltage drop across the sense resistor. A comparator detects this condition and turns both FETs on. The rectifier is then conductive, so current can flow from the anode terminal, through the larger FET1, and to the cathode terminal, with a small forward voltage drop and without passing across the sense resistor.

公开(公告)号：US09054587B2

公开(公告)日：2015-06-09

申请号：US14152989

申请日：2014-01-10

申请人： IXYS Corporation

发明人： Leonid A. Neyman

IPC分类号： H02J7/00 ,  H02M7/217 ,  H02M1/00

CPC分类号： H02M7/2176 ,  H02M2001/0006

摘要： In a steady state operation mode, a charging circuit of a non-isolated AC-to-DC converter decouples an output voltage VO node from a VR node when the rectifier output signal VR on the VR node is greater than a first predetermined voltage VP and, 2) supplies a charging current from the VR node and onto the VO node when VR is less than VP provided that an output voltage VO on the VO node is less than a second predetermined voltage VO(MAX) and provided that VR is greater than VO. In an initial power up operation mode, the maximum limit value of the charging current is smaller than it is during steady state operation. Due to the reduced charging currents employed during initial power up operation, less noise is injected back to the AC source and EMI filters are not required between the rectifier of the converter and the AC source.

摘要翻译： 在稳态运行模式中，当VR节点上的整流器输出信号VR大于第一预定电压VP时，非隔离AC-DC转换器的充电电路将输出电压VO节点与VR节点分离， ，2）当VR小于VP时，从VR节点向VO节点提供充电电流，只要VO节点上的输出电压VO小于第二预定电压VO（MAX），并且假定VR大于 VO。 在初始上电操作模式中，充电电流的最大极限值小于稳态操作期间的最大限制值。 由于在初始上电操作期间采用的充电电流降低，较少的噪声被注入到AC电源，并且在转换器的整流器和AC电源之间不需要EMI滤波器。

公开(公告)号：US20180219532A1

公开(公告)日：2018-08-02

申请号：US15423421

申请日：2017-02-02

申请人： IXYS Corporation

发明人： Anatoliy V. Tsyrganovich ,  Leonid A. Neyman

IPC分类号： H03K3/012 ,  H03K19/0185

CPC分类号： H03K3/012 ,  H03K17/687 ,  H03K19/018507 ,  H03K2217/0063

摘要： A gate driver integrated circuit drives an output signal onto its output terminal and onto the gate of a power transistor. In a turn-on episode, a digital input signal transitions to a digital logic high level. In response, the gate driver integrated circuit couples the output terminal to a positive supply voltage terminal, thereby driving a positive voltage onto the gate of the power transistor. In response to a high-to-low transition of the digital input signal, the driver drives a negative voltage onto the output terminal and power transistor gate for a short self-timed period of time, and then couples the output terminal to a ground terminal, thereby driving the output terminal and power transistor gate up to ground potential. The output terminal and power transistor gate are then held at ground potential in anticipation of the next turn-on episode of the power transistor.

公开(公告)号：US09571003B2

公开(公告)日：2017-02-14

申请号：US14700431

申请日：2015-04-30

申请人： IXYS Corporation

发明人： Leonid A. Neyman

IPC分类号： H02J7/00 ,  H02M7/217

CPC分类号： H02M7/217 ,  H02M7/2176 ,  H02M2001/0006

摘要： Within a non-isolated and efficient AC-to-DC power supply circuit: 1) a dep-FET is turned off to decouple an output voltage VO node from a VR node when a rectifier output signal VR on the VR node is greater than a first predetermined voltage VP and, 2) the dep-FET is enabled to be turned on so that a constant charging current flows from the VR node and onto the VO node when VR is less than VP (provided that VO is less than a second predetermined voltage VO(MAX) and provided that VR is adequately greater than VO). To speed turn off and on of the dep-FET, gate charge of the dep-FET is removed and is stored in a second capacitor when the dep-FET is to be turned off, and charge from the second capacitor is moved back onto the gate of the dep-FET when the dep-FET is to be turned on.

摘要翻译： 在非隔离且高效的AC至DC电源电路中：1）当VR节点上的整流器输出信号VR大于一个时，去极FET被截止以将输出电压VO节点与VR节点去耦 第一预定电压VP，以及2）使得能够导通去FET，使得当VR小于VP时，恒定的充电电流从VR节点流到VO节点（假设VO小于第二预定电压VP 电压VO（MAX），并且假设VR足够大于VO）。 为了加速去FET的关闭和导通，去FET的栅极电荷被去除，并且当去FET被截止时将其存储在第二电容器中，并且来自第二电容器的电荷被移回到 当去FET被接通时，FET的栅极。

公开(公告)号：US10069485B2

公开(公告)日：2018-09-04

申请号：US15423421

申请日：2017-02-02

申请人： IXYS Corporation

发明人： Anatoliy V. Tsyrganovich ,  Leonid A. Neyman

IPC分类号： H03K3/012 ,  H03K19/0185

CPC分类号： H03K19/018507 ,  H03K17/687 ,  H03K2217/0063

摘要： A gate driver integrated circuit drives an output signal onto its output terminal and onto the gate of a power transistor. In a turn-on episode, a digital input signal transitions to a digital logic high level. In response, the gate driver integrated circuit couples the output terminal to a positive supply voltage terminal, thereby driving a positive voltage onto the gate of the power transistor. In response to a high-to-low transition of the digital input signal, the driver drives a negative voltage onto the output terminal and power transistor gate for a short self-timed period of time, and then couples the output terminal to a ground terminal, thereby driving the output terminal and power transistor gate up to ground potential. The output terminal and power transistor gate are then held at ground potential in anticipation of the next turn-on episode of the power transistor.

公开(公告)号：US09705417B2

公开(公告)日：2017-07-11

申请号：US14955037

申请日：2015-11-30

申请人： IXYS Corporation

发明人： Anatoliy V. Tsyrganovich ,  Leonid A. Neyman

IPC分类号： H02M7/217 ,  H02M7/219

CPC分类号： H02M7/219 ,  H02M2007/2195 ,  Y02B70/1408

摘要： A rectifier includes a larger Field Effect Transistor (FET1) and a smaller FET (FET2). A sense resistor is in series with FET2's body diode between a cathode terminal and an anode terminal. If the cathode terminal voltage is greater than the voltage on the anode terminal, then body diodes of FETs are reverse biased, the FETs are controlled to be off, and there is no current flow through the rectifier. If, however, the voltage on the anode terminal becomes positive with respect to the cathode terminal, then the body diode of FET2 starts to conduct and there is a voltage drop across the sense resistor. A comparator detects this condition and turns both FETs on. The rectifier is then conductive, so current can flow from the anode terminal, through the larger FET1, and to the cathode terminal, with a small forward voltage drop and without passing across the sense resistor.

公开(公告)号：US09089025B2

公开(公告)日：2015-07-21

申请号：US13647139

申请日：2012-10-08

申请人： IXYS Corporation

发明人： Leonid A. Neyman ,  Allan Ming-Lun Lin

IPC分类号： H05B41/16 ,  H05B33/08 ,  H03K7/08 ,  H05B37/02 ,  H04L25/49

CPC分类号： H05B33/0818 ,  H03K7/08 ,  H04L25/4902 ,  H05B37/0254 ,  Y02B20/346

摘要： A system for communicating with a host using control signals over a 1-wire interface is disclosed. The system includes a driver coupled to the host by the 1-wire interface. Control signals are transmitted from the host to the driver for decoding by the driver controller. The control signals are pulse width modulation format signals which are interpreted by the driver as binary encoded command mode signals or analog encoded command mode signals, depending upon when the signals are received in relation to a preamble pulse and a post-amble pulse.

摘要翻译： 公开了一种使用1线接口的控制信号与主机进行通信的系统。 该系统包括通过1线接口耦合到主机的驱动器。 控制信号从主机发送到驱动器，由驱动器控制器进行解码。 控制信号是脉冲宽度调制格式信号，由驱动器解释为二进制编码命令模式信号或模拟编码命令模式信号，这取决于何时相对于前导脉冲和后导后脉冲接收信号。

公开(公告)号：US20140126258A1

公开(公告)日：2014-05-08

申请号：US14152989

申请日：2014-01-10

申请人： IXYS Corporation

发明人： Leonid A. Neyman

IPC分类号： H02M7/06

CPC分类号： H02M7/2176 ,  H02M2001/0006

摘要： In a steady state operation mode, a charging circuit of a non-isolated AC-to-DC converter decouples an output voltage VO node from a VR node when the rectifier output signal VR on the VR node is greater than a first predetermined voltage VP and, 2) supplies a charging current from the VR node and onto the VO node when VR is less than VP provided that an output voltage VO on the VO node is less than a second predetermined voltage VO(MAX) and provided that VR is greater than VO. In an initial power up operation mode, the maximum limit value of the charging current is smaller than it is during steady state operation. Due to the reduced charging currents employed during initial power up operation, less noise is injected back to the AC source and EMI filters are not required between the rectifier of the converter and the AC source.

摘要翻译： 在稳态运行模式中，当VR节点上的整流器输出信号VR大于第一预定电压VP时，非隔离AC-DC转换器的充电电路将输出电压VO节点与VR节点分离， ，2）当VR小于VP时，从VR节点向VO节点提供充电电流，只要VO节点上的输出电压VO小于第二预定电压VO（MAX），并且假定VR大于 VO。 在初始上电操作模式中，充电电流的最大极限值小于稳态操作期间的最大限制值。 由于在初始上电操作期间采用的充电电流降低，较少的噪声被注入到AC电源，并且在转换器的整流器和AC电源之间不需要EMI滤波器。

公开(公告)号：US20150236613A1

公开(公告)日：2015-08-20

申请号：US14700431

申请日：2015-04-30

申请人： IXYS Corporation

发明人： Leonid A. Neyman

IPC分类号： H02M7/217

CPC分类号： H02M7/217 ,  H02M7/2176 ,  H02M2001/0006

摘要： Within a non-isolated and efficient AC-to-DC power supply circuit: 1) a dep-FET is turned off to decouple an output voltage VO node from a VR node when a rectifier output signal VR on the VR node is greater than a first predetermined voltage VP and, 2) the dep-FET is enabled to be turned on so that a constant charging current flows from the VR node and onto the VO node when VR is less than VP (provided that VO is less than a second predetermined voltage VO(MAX) and provided that VR is adequately greater than VO). To speed turn off and on of the dep-FET, gate charge of the dep-FET is removed and is stored in a second capacitor when the dep-FET is to be turned off, and charge from the second capacitor is moved back onto the gate of the dep-FET when the dep-FET is to be turned on.

摘要翻译： 在非隔离且高效的AC至DC电源电路中：1）当VR节点上的整流器输出信号VR大于一个时，去极FET被截止以将输出电压VO节点与VR节点去耦 第一预定电压VP，以及2）使得能够导通去FET，使得当VR小于VP时，恒定的充电电流从VR节点流到VO节点（假设VO小于第二预定电压VP 电压VO（MAX），并且假设VR足够大于VO）。 为了加速去FET的关闭和导通，去FET的栅极电荷被去除，并且当去FET被截止时将其存储在第二电容器中，并且来自第二电容器的电荷被移回到 当去FET被接通时，FET的栅极。

公开(公告)号：US20130028338A1

公开(公告)日：2013-01-31

申请号：US13647139

申请日：2012-10-08

申请人： IXYS Corporation

发明人： Leonid A. Neyman ,  Allan Ming-Lun Lin

IPC分类号： H04L25/00

CPC分类号： H05B33/0818 ,  H03K7/08 ,  H04L25/4902 ,  H05B37/0254 ,  Y02B20/346

摘要： A system for communicating with a host using control signals over a 1-wire interface is disclosed. The system includes a driver coupled to the host by the 1-wire interface. Control signals are transmitted from the host to the driver for decoding by the driver controller. The control signals are pulse width modulation format signals which are interpreted by the driver as binary encoded command mode signals or analog encoded command mode signals, depending upon when the signals are received in relation to a preamble pulse and a post-amble pulse.

摘要翻译： 公开了一种使用1线接口的控制信号与主机进行通信的系统。 该系统包括通过1线接口耦合到主机的驱动器。 控制信号从主机发送到驱动器，由驱动器控制器进行解码。 控制信号是脉冲宽度调制格式信号，由驱动器解释为二进制编码命令模式信号或模拟编码命令模式信号，这取决于何时相对于前导脉冲和后导后脉冲接收信号。