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1.发明授权Signal processor for rapidly calculating a predetermined calculation a plurality of times to typically carrying out FFT or inverse FFT 失效用于快速计算预定计算多次以通常执行FFT或逆FFT的信号处理器
公开(公告)号：US4899301A
公开(公告)日：1990-02-06
申请号：US8684
申请日：1987-01-29
申请人： Takao Nishitani , Yuichi Kawakami , Hideo Tanaka , Ichiro Kuroda
发明人： Takao Nishitani , Yuichi Kawakami , Hideo Tanaka , Ichiro Kuroda
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： In a signal processor for processing zeroth through (N-1)-th input signal elements into zeroth through (N-1)-th output signal elements, the input elements are initially stored, as memorized data, in respective memory addresses of a memory arrangement (11, 12) by a memory accessing arrangement which comprises a first address calculating arrangement (311, 321) for calculating a first address for the memory addresses. A distance indicating arrangement (312, 322) is for indicating an address distance from the first address among the memory addresses. By using the first address and the address distance a second address is calculated by a second address calculating arrangement (313, 323). A pair of stored data are read from the first and the second addresses as a pair of read data. A calculation performing circuit (20) is for performing a predetermined calculation on the pair of read data by using a coefficient read from a read-only memory (14) to produce a pair of calculated data which are stored in the first and the second addresses as the stored data. The calculation performing circuit performs the predetermined calculation a plurality of times to produce the output elements.
摘要翻译： 在用于将第（N-1）个第（N-1）个输入信号元素处理为第零到第（N-1）个输出信号元件的信号处理器中，输入元件最初作为存储的数据存储在存储器的相应存储器地址中 存储器访问装置（11,12）包括用于计算存储器地址的第一地址的第一地址计算装置（311,321）。 距离指示装置（312,322）用于指示存储器地址中与第一地址的地址距离。 通过使用第一地址和地址距离，第二地址由第二地址计算装置（313,323）计算。 从第一和第二地址读取一对存储的数据作为一对读取数据。 计算执行电路（20）用于通过使用从只读存储器（14）读取的系数来对该对读取数据执行预定计算，以产生存储在第一和第二地址中的一对计算数据 作为存储的数据。 计算执行电路多次执行预定的计算以产生输出元件。
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公开(公告)号：US4722068A
公开(公告)日：1988-01-26
申请号：US727020
申请日：1985-04-25
申请人： Ichiro Kuroda , Takao Nishitani , Hideo Tanaka , Yuichi Kawakami
发明人： Ichiro Kuroda , Takao Nishitani , Hideo Tanaka , Yuichi Kawakami
CPC分类号： G06F7/5324 , G06F2207/382
摘要： A double precision multiplyer for performing the multiplication of two double precision data using a 2's complement single precision multiplier. The 2n-1 bit double precision data is divided into one single precision data formed by taking the upper n bits of the double precision data and another single precision data formed by adding a "0" bit before the most significant bit of the remaining n-1 bits of the double precision data. Apparatus for performing the double precision multiplication thereby eliminates the necessity of discriminating the sign bit and enhances the speed of the double precision multiplication.
摘要翻译： 双精度乘法器，用于使用2的补码单精度乘数执行两个双精度数据的乘法。 2n-1位双精度数据被分成通过取高精度数据的高n位形成的一个单精度数据，另一个单精度数据通过在剩余的n位精度数据的最高有效位之前加上“0” 1位双精度数据。 用于执行双精度乘法的装置消除了识别符号位的必要性，并提高双精度倍增的速度。
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公开(公告)号：US4817047A
公开(公告)日：1989-03-28
申请号：US883703
申请日：1986-07-09
CPC分类号： G06F7/5443 , G06F17/10 , G06F7/49921
摘要： A digital signal processing circuit reduces the occurrence of overflow conditions during successive arithmetic operations. The product output of a multiplication circuit is shifted by a barrel shifter to round off a predetermined number of least significant bits, thereby reducing the occurrence of an overflow condition when the successive product outputs of the multiplication circuit are summed by an arithmetic logic unit (ALU) to produce a summed output. The summed output is then shifted toward the most significant bit by a predetermined number before an output signal is generated. An overflow detection and correction circuit is provided in the event of an overflow condition occurring either to the ALU or the barrel shifter.
摘要翻译： 数字信号处理电路在连续的算术运算期间减少了溢出状况的发生。 乘法电路的乘积输出由桶形移位器移位以舍弃预定数量的最低有效位，从而当乘法电路的连续乘积输出由算术逻辑单元（ALU）相加时减少溢出状况的发生 ）产生一个总和输出。 然后，在产生输出信号之前，将相加的输出向最高有效位移位预定数。 在ALU或桶形移位器发生溢出状况的情况下，提供溢出检测和校正电路。
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公开(公告)号：US4571737A
公开(公告)日：1986-02-18
申请号：US558236
申请日：1983-12-05
申请人： Takao Nishitani , Ichiro Kuroda , Tadaharu Kato
发明人： Takao Nishitani , Ichiro Kuroda , Tadaharu Kato
摘要： In an APDCM decoding circuit, an adaptive inverse quantizer which forms a quantized coded signal, produces a residual signal and upper and lower limits thereof. An adaptive prediction circuit uses the residual signal to predict a quantization, which is added to the other signals. The added residual is converted into a nonlinear encoded PCM for output. However the output is PCM linearized and compared to the added upper and lower limits to determine if the output should be incremented or decremented.
摘要翻译： 在APDCM解码电路中，形成量化编码信号的自适应逆量化器产生残留信号及其上限和下限。 自适应预测电路使用残差信号预测加到其他信号的量化。 将附加的残差转换为非线性编码的PCM进行输出。 然而，输出是PCM线性化的，并与添加的上限和下限进行比较，以确定输出是否应该递增或递减。
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公开(公告)号：US4811268A
公开(公告)日：1989-03-07
申请号：US864268
申请日：1986-05-19
申请人： Takao Nishitani , Yuichi Kawakami
发明人： Takao Nishitani , Yuichi Kawakami
CPC分类号： G06F7/5443 , G06F17/10 , G06F7/49921
摘要： In a processing circuit for successively accumulating a first predetermined number of products, each product is shifted in a barrel shifter (20) downwards by a second predetermined number of bits determined in relation to the first predetermined number and is successively added to a previous result of accumulation in an arithmetic/logic unit (ALU) (21) the first predetermined number of times to produce a final result of accumulation. The first result is shifted in a shifter (27) upwards by a third predetermined number of bits determined in relation to the second predetermined number. An overflow detector (26) monitors each result of accumulation to detect occurrence of an overflow in the ALU and the shifter to substitute either a positive or a negative maximum number for each result by an overflow corrector (25) on occurrence of the overflow. The substituted maximum number or the shifted final result is produced as an output signal.
摘要翻译： 在用于连续地累积第一预定数量的乘积的处理电路中，每个乘积在桶形移位器（20）中向下移动相对于第一预定数量确定的第二预定数量的位，并被连续地添加到 在算术/逻辑单元（ALU）（21）中积累第一预定次数以产生累积的最终结果。 第一结果在移位器（27）中向上移动相对于第二预定数确定的第三预定数量的位。 溢出检测器（26）监视每个累积结果，以检测ALU和移位器中的溢出的发生，以便在出现溢出时由溢出校正器（25）替换每个结果的正或负最大数目。 取代的最大数量或移位的最终结果作为输出信号产生。
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公开(公告)号：US4379338A
公开(公告)日：1983-04-05
申请号：US209250
申请日：1980-11-21
申请人： Takao Nishitani , Yuichi Kawakami
发明人： Takao Nishitani , Yuichi Kawakami
CPC分类号： G06F7/5095 , G06F7/4991
摘要： Overflow monitoring circuitry for an arithmetic unit offsets consecutive positive and negative overflows against one another to eliminate unnecessary overflow compensation during an arithmetic operation. In a first embodiment, an up/down counter is used to count positive overflows in one direction and negative overflows in another, with the value of the counter at the end of the arithmetic operation indicating the net overflow, if any has occurred, and the most significant bit of the counter representing the direction of any net overflow. In a second embodiment, logic circuitry offsets alternate positive and negative overflows against one another but will provide an overflow signal if either an odd number of overflows occurs or if two consecutive overflows in one direction occur during the arithmetic operation.
摘要翻译： 运算单元的溢出监控电路将连续的正和负溢出相互抵消，以在算术运算期间消除不必要的溢出补偿。 在第一实施例中，使用向上/向下计数器对一个方向上的正溢出进行计数，并在另一方向上计数负溢出，而在算术运算结束时的计数器的值表示净溢出（如果有的话），并且 计数器的最高有效位表示任何净溢出的方向。 在第二实施例中，逻辑电路相互抵消交替的正和负溢出，但是如果发生奇数个溢出或者在算术运算期间发生两个连续的一个方向溢出，则会提供溢出信号。
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7.发明授权
公开(公告)号：US4796218A
公开(公告)日：1989-01-03
申请号：US16036
申请日：1987-02-18
申请人： Hideo Tanaka , Takao Nishitani
发明人： Hideo Tanaka , Takao Nishitani
CPC分类号： G06F7/483 , G06F7/49936
摘要： An arithmetic circuit comprises a pair of input registers for holding a pair of given numbers, and a radix point adjustment circuit coupled to the input registers for aligning the radix points of the given numbers. This adjsutment circuit is capable of outputting at least a pair of radix point aligned fractions and one exponent derived from the radix point alignment. An arithmetic operation circuit receives the pair of the radix point aligned fractions, and outputs the result of a given arithmetic operation of the received fractions and generates an overflow signal when an overflow is generated in the arithmetic operation of the received fractions. An exponent correction circuit receives the exponent from the adjustment circuit, and is responsive to the overflow signal from the arithmetic operation circuit so as to selectively correct the received exponent. A fraction correction circuit receives the output of the arithmetic operation circuit so as to correct the received data. There is provided a first selector receiving the output of the exponent correction circuit and responsive to a given control signal so as to selectively output the output of the exponent correction circuit or a predetermined value. Further, a second selector is provided to receive the outputs of the arithmetic operation circuit and the fraction correction circuit so as to selectively output one of the two received fractions in response to the control signal.
摘要翻译： 运算电路包括一对用于保持一对给定数字的输入寄存器，以及耦合到输入寄存器的基数点调整电路，用于对准给定数字的小数点。 该调整电路能够输出至少一对小数点对齐分数和从小数点对齐导出的一个指数。 算术运算电路接收一对基点对齐分数，并输出接收分数的给定算术运算结果，并在接收分数的算术运算中产生溢出时产生溢出信号。 指数校正电路从调整电路接收指数，并响应于来自算术运算电路的溢出信号，以选择性地校正接收指数。 分数校正电路接收算术运算电路的输出，以校正接收到的数据。 提供了接收指数校正电路的输出并响应于给定控制信号的第一选择器，以选择性地输出指数校正电路的输出或预定值。 此外，提供第二选择器以接收算术运算电路和分数校正电路的输出，以便响应于控制信号选择性地输出两个接收分数中的一个。
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8.发明授权
公开(公告)号：US4554670A
公开(公告)日：1985-11-19
申请号：US484676
申请日：1983-04-13
申请人： Shinichi Aiko , Rikio Maruta , Takao Nishitani
发明人： Shinichi Aiko , Rikio Maruta , Takao Nishitani
CPC分类号： H03M3/042
摘要： An adaptive differential pulse code modulated (ADPCM) transmission system includes a subtractor for providing a difference signal E.sub.j between an input signal X.sub.j and a predicted signal X.sub.j. A coder encodes the difference signal E.sub.j into a coded signal U.sub.j for transmission to a receiver. The signal U.sub.j is also decoded at the transmitter to produce a reproduced error signal E.sub.j. A prediction circuit operates to generate a prediction signal X.sub.j on the basis of the reproduced error signal E.sub.j. The prediction circuit is controlled by a control circuit which operates to detect transmitter instability. A first level detector in the control circuit compares the input signal level against the level of a transmitter produced signal representing the input signal. A second level detector of the control circuit determines when the input signal is below a specified value. Transmitter instability is judged by a decision circuit which determines when the output of the first level detector exceeds a preset value and the output of the second level detector is below another preset value.
摘要翻译： 自适应差分脉冲编码调制（ADPCM）传输系统包括用于在输入信号Xj和预测信号Xj之间提供差分信号Ej的减法器。 编码器将差分信号Ej编码为编码信号Uj以传送到接收机。 在发射机处也对信号Uj进行解码以产生再现的误差信号Ej。 预测电路用于根据再现的误差信号Ej产生预测信号Xj。 预测电路由操作以检测发射机不稳定性的控制电路控制。 控制电路中的第一电平检测器将输入信号电平与表示输入信号的发射机产生信号的电平进行比较。 控制电路的第二电平检测器确定输入信号何时低于规定值。 发射机不稳定性由判定电路判定，判定电路确定第一电平检测器的输出何时超过预设值，第二电平检测器的输出低于另一预定值。
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9.发明授权Sampled data processing system having memory with areas alternately dedicated to data I/O and data processing 失效具有交替专用于数据I / O和数据处理的区域的存储器的采样数据处理系统
公开(公告)号：US4287558A
公开(公告)日：1981-09-01
申请号：US944635
申请日：1978-09-21
申请人： Takao Nishitani
发明人： Takao Nishitani
CPC分类号： G06F13/1673 , G01S7/2806 , G06F13/282
摘要： A system for processing data received in the form of sample pulses has a memory with first and second major memory areas. A buffer register stores data temporarily to enable an interface between the timing of the system and of a sampled analog signal. A central processor processes data stored in one major memory area while data stored in the other major memory area is being transferred between the memory and the buffer register. The data transfer occurs during time periods while the central processor does not have access to the memory. One data item is outputted for each sample pulse received. This way, the cycle time of the sample pulses may be much greater than the cycle time of the central processor.
摘要翻译： 用于处理以采样脉冲形式接收的数据的系统具有具有第一和第二主存储区的存储器。 缓冲寄存器临时存储数据，以实现系统定时和采样模拟信号之间的接口。 中央处理器处理存储在一个主存储区中的数据，而存储在另一个主存储区中的数据正在存储器和缓冲寄存器之间传送。 数据传输发生在中央处理器无法访问存储器的时间段内。 对于接收到的每个采样脉冲输出一个数据项。 这样，采样脉冲的周期时间可能远大于中央处理器的周期时间。
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公开(公告)号：US4700392A
公开(公告)日：1987-10-13
申请号：US643929
申请日：1984-08-24
申请人： Tadaharu Kato , Takao Nishitani
发明人： Tadaharu Kato , Takao Nishitani
CPC分类号： G10L25/78
摘要： Speech presence is detected by first comparing input signal absolute value versus a first threshold which is proportional to input signal RMS noise power, accumulating the first comparison output signal, then comparing the accumulated signal versus a second threshold signal which is proportional to a hangover time signal. The first and second threshold signals are used to form up to six threshold values.
摘要翻译： 通过首先比较输入信号绝对值与与输入信号RMS噪声功率成比例的第一阈值来检测语音存在，累积第一比较输出信号，然后比较累积信号与延时时间信号成比例的第二阈值信号 。 第一和第二阈值信号用于形成多达六个阈值。
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