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1.发明授权
公开(公告)号：US4554670A
公开(公告)日：1985-11-19
申请号：US484676
申请日：1983-04-13
申请人： Shinichi Aiko , Rikio Maruta , Takao Nishitani
发明人： Shinichi Aiko , Rikio Maruta , Takao Nishitani
CPC分类号： H03M3/042
摘要： An adaptive differential pulse code modulated (ADPCM) transmission system includes a subtractor for providing a difference signal E.sub.j between an input signal X.sub.j and a predicted signal X.sub.j. A coder encodes the difference signal E.sub.j into a coded signal U.sub.j for transmission to a receiver. The signal U.sub.j is also decoded at the transmitter to produce a reproduced error signal E.sub.j. A prediction circuit operates to generate a prediction signal X.sub.j on the basis of the reproduced error signal E.sub.j. The prediction circuit is controlled by a control circuit which operates to detect transmitter instability. A first level detector in the control circuit compares the input signal level against the level of a transmitter produced signal representing the input signal. A second level detector of the control circuit determines when the input signal is below a specified value. Transmitter instability is judged by a decision circuit which determines when the output of the first level detector exceeds a preset value and the output of the second level detector is below another preset value.
摘要翻译： 自适应差分脉冲编码调制（ADPCM）传输系统包括用于在输入信号Xj和预测信号Xj之间提供差分信号Ej的减法器。 编码器将差分信号Ej编码为编码信号Uj以传送到接收机。 在发射机处也对信号Uj进行解码以产生再现的误差信号Ej。 预测电路用于根据再现的误差信号Ej产生预测信号Xj。 预测电路由操作以检测发射机不稳定性的控制电路控制。 控制电路中的第一电平检测器将输入信号电平与表示输入信号的发射机产生信号的电平进行比较。 控制电路的第二电平检测器确定输入信号何时低于规定值。 发射机不稳定性由判定电路判定，判定电路确定第一电平检测器的输出何时超过预设值，第二电平检测器的输出低于另一预定值。
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2.发明授权2M-point discrete Fourier transform calculator comprising a pre-processor for twice performing extraction of conjugate symmetric and/or antisymmetric components 失效2M点离散付里叶变换计算器，包括用于两次执行共轭对称和/或反对称分量的提取的预处理器
公开(公告)号：US4164021A
公开(公告)日：1979-08-07
申请号：US839537
申请日：1977-10-05
申请人： Takao Nishitani , Rikio Maruta
发明人： Takao Nishitani , Rikio Maruta
CPC分类号： G06F17/141
摘要： An N-point DFT (discrete Fourier transform) calculator comprises a pre-processor responsive to N-point complex input data F.sub.k (k=0 to N-1) for producing N/2-point complex intermediate data G.sub.p (p=0 to N/2-1) and an N/2-point DFT calculating circuit supplied with the intermediate data as N/2-point complex input data for producing in a known manner real and imaginary parts g.sub.q.sup.R and g.sub.q.sup.I of DFT's or IDFT's (inverse DFT) g.sub.q (q=0 to N/2-1) of the latter input data G.sub.p as either real or imaginary parts f.sub.n.sup.R or f.sub.n.sup.I (n=0 to N-1) of even and odd numbered DFT's or IDFT's f.sub.2n' and f.sub.2n'+1 (n'=0 to N/2-1) of the original input data F.sub.k. The pre-processor extracts from the input data F.sub.k a truncated sequence of conjugate symmetric or antisymmetric components H.sub.m, N/2+1 in number, extracts from the truncated sequence conjugate symmetric and antisymmetric components A.sub.p and B.sub.p, [N/4]+1 in number where the brackets are the Gauss' notation, and calculates complex products of ones of the latter components A.sub.p or B.sub.p and factors, such as jexp(-j[2.pi./N]p) for DFT's or jexp(j[2.pi./N]p) for IDFT's, sums of the products and the others of the latter components B.sub.p or A.sub.p, differences between the products and the others B.sub.p or A.sub.p, and conjugate complex data of the differences. For the real parts f.sub.n.sup.R, the sums and the conjugate complex data provide the intermediate data. For the imaginary parts f.sub.n.sup.I, the differences are used instead of the sums. For factors exp(-j[2.pi./N]p) or exp(j[2.pi./N]p), each of the other components B.sub.p or A.sub.p should include a factor j.
摘要翻译： N点DFT（离散傅里叶变换）计算器包括响应于N点复数输入数据F k（k = 0至N-1）的预处理器，用于产生N / 2点复数中间数据Gp（p = 0至 N / 2-1）和提供有中间数据的N / 2点DFT计算电路作为N / 2点复数输入数据，用于以已知方式产生DFT或IDFT的实部和qq的虚部gqR和反向DFT ）后一个输入数据Gp的gq（q = 0到N / 2-1）作为偶数和奇数DFT或IDFT的f2n'和f2n'的实部或虚部fnR或fnI（n = 0到N-1） +1（n'= 0〜N / 2-1）原始输入数据Fk。 预处理器从输入数据Fk提取数字的共轭对称或反对称分量Hm，N / 2 + 1的截断序列，从截断序列共轭对称和反对称分量Ap和Bp提取[N / 4] +1 其中括号是高斯符号，并且计算后一个组分Ap或Bp中的一个的复合乘积和诸如jexp（-j [2 pi / N] p）的因子，对于DFT或jexp（j [2 pi / N] p），产品与其后的组分Bp或Ap的总和，产品与其他Bp或Ap之间的差异，以及差异的共轭复数数据。 对于实部fnR，求和和复共轭数据提供中间数据。 对于虚部fnI，使用差异而不是总和。 对于因子exp（-j [2 pi / N] p）或exp（j [2 pi / N] p），其他分量Bp或Ap中的每一个应包括因子j。
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公开(公告)号：US4467315A
公开(公告)日：1984-08-21
申请号：US934985
申请日：1978-08-18
申请人： Rikio Maruta , Atsushi Tomozawa
发明人： Rikio Maruta , Atsushi Tomozawa
摘要： A compandor converts a linear code signal consisting of a polarity bit and a plurality of absolute value bits. The polarity bit represents the polarity of each sample value of an original analog signal. The absolute value bits represent the absolute value of the sample. The compandor converts the linear code into a nonlinear code including the polarity bit, a plurality of segment bits representing the segments in a characteristic curve to which the original analog signal belongs, and mantissa bits which indicate the position of the sample value in that segment. The compandor comprises: a plurality of input terminals for receiving the linear code signal; a first read-only memory means, addressed by a first bit group among the absolute value bits for memorizing a segment bit decision rule; a second read-only memory means, addressed by a second bit group consisting of another plurality of bits among the absolute value bits and some bits in common with the first bit group for memorizing a first mantissa bit decision rule; a third read-only memory means, addressed by the first bit group, for memorizing a second mantissa bit decision rule; and means for selecting the second or third read-only memory means depending on the value of the most significant bit among the segment bits applied from the first read-only memory means.
摘要翻译： 压缩器转换由极性位和多个绝对值位组成的线性码信号。 极性位表示原始模拟信号的每个采样值的极性。 绝对值位代表样本的绝对值。 压缩器将线性代码转换为非线性代码，其包括极性位，表示原始模拟信号所属的特性曲线中的段的多个段位以及指示该段中的采样值的位置的尾数位。 该压缩器包括：用于接收线性码信号的多个输入端; 第一只读存储器装置，用于存储段位决定规则的绝对值位之中的第一位组寻址; 第二只读存储器装置，由绝对值位中的另外多个位组成的第二位组寻址，以及与用于存储第一尾数位决定规则的第一位组共同的一些位; 由第一位组寻址的用于存储第二尾数位决定规则的第三只读存储器装置; 以及用于根据从第一只读存储器装置施加的段比特中的最高有效位的值来选择第二或第三只读存储器装置的装置。
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公开(公告)号：US5144620A
公开(公告)日：1992-09-01
申请号：US478879
申请日：1990-02-08
摘要： An internal frame signal producing circuit for use in a cross connection system which cross connects first bit rate signals, each produced by multiplexing m second bit rate signals at first or the second bit rate signal levels, the first bit rate being higher than the second bit rate, an internal frame frequency is predetermined to be equal to a frequency f.sub.h ' higher than a first nominal frequency f.sub.h of the first bit rate digital signals by a predetermined value, the frequency f.sub.h ' being synchronized with a second nominal frequency fl of the second bit rate digital signals. In order to obtain the internal frame signal, from m second bit rate signals, the m second bit rate signals are stuff-synchronized processed to produce m stuff-synchronized signals, each having a stuff bit, a variable bit, and vacant bit at suitable bit intervals in a frame of a frame length. The m stuffed-synchronized signals are serially arranged to make the internal frame signal. In order to compensate a frequency difference between f.sub.h ' and fl, one frame consisting of all vacant bits is assigned at predetermined frame intervals.
摘要翻译： 一种在交叉连接系统中使用的内部帧信号产生电路，其交叉连接第一比特率信号，每个第一比特率信号通过首先复用m个第二比特率信号或第二比特率信号电平而产生，第一比特率高于第二比特率 将内部帧频预定为等于比第一比特率数字信号的第一标称频率fh高出预定值的频率fh'，频率fh'与第二位速率数字信号的第二标称频率f1同步 比特率数字信号。 为了获得内部帧信号，从m个第二比特率信号中，m个第二比特率信号被填充同步处理以产生m个同步信号，每个信号具有适当的填充位，可变位和空闲位 帧长度的帧中的位间隔。 m个填充同步信号被串行排列以产生内部帧信号。 为了补偿fh'和fl之间的频率差异，以预定的帧间隔分配由所有空位组成的一帧。
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公开(公告)号：US4097860A
公开(公告)日：1978-06-27
申请号：US766848
申请日：1977-02-09
申请人： Takashi Araseki , Kazuo Ochiai , Rikio Maruta
发明人： Takashi Araseki , Kazuo Ochiai , Rikio Maruta
CPC分类号： H03M1/1295
摘要： Method and apparatus for cancelling a deviation in an input signal due to drift, line or background noise, changes in circuit component characteristics due to aging, and the like wherein the input signal, typically a digitized representation of an analog signal, is altered by a presumed offset magnitude; the polarity of the difference is monitored and a negative or positive count of clock pulses is accumulated dependent upon the aforesaid polarity. When a determined positive (or negative) count is reached the presumed offset is adjusted (up or down) by a predetermined increment and the count is begun anew. As an alternative technique and embodiment the initiation of the count may be restrained as long as the magnitude of the digitized input signal exceeds a predetermined threshold.
摘要翻译： 用于消除由漂移，线路或背景噪声引起的输入信号偏差的方法和装置，由于老化引起的电路元件特性的变化等，其中输入信号（通常是模拟信号的数字化表示）被改变为 推定偏移量; 监视差异的极性，并根据上述极性累积时钟脉冲的负数或正数。 当达到确定的正（或负）计数时，推定的偏移量被调整（向上或向下）预定的增量，并且重新开始计数。
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公开(公告)号：US4392234A
公开(公告)日：1983-07-05
申请号：US261923
申请日：1981-05-08
申请人： Rikio Maruta
发明人： Rikio Maruta
CPC分类号： H04J4/005 , H04J3/0626
摘要： A PCM signal interface apparatus comprises a buffer memory being capable of asynchronously writing and reading a PCM signal, means for inserting a frame marker to the PCM signal upon writing the PCM signal into the buffer memory, means for judging whether or not the frame marker is contained in an output signal read out of the buffer memory at a time that is designated by an external read frame position designating pulse, means for resetting all the contents in the buffer memory and temporarily stopping the supply of a writing clock and a reading clock to the buffer memory when the frame marker is not delivered out at the predetermined time, means for resuming the supply of the writing clock to the buffer memory by receiving a write frame position designating pulse, and means for resuming the supply of the reading clock to the buffer memory by receiving the frame position designating pulse at a predetermined time lapse after the resumption of the writing clock supply. The data written into the buffer memory can be read out at a desired frame phase and data speed without duplication and missing of the read data.
摘要翻译： PCM信号接口装置包括能够异步写入和读取PCM信号的缓冲存储器，用于在将PCM信号写入缓冲存储器时将帧标记插入PCM信号的装置，用于判断帧标记是否为 包含在由外部读取帧位置指定脉冲指定的时间从缓冲存储器读出的输出信号中的装置，用于复位缓冲存储器中的所有内容并暂时停止写入时钟和读取时钟的提供的装置 当帧标记在预定时间没有被输出时的缓冲存储器，用于通过接收写入帧位置指定脉冲来恢复向缓冲存储器提供写入时钟的装置，以及用于恢复将读取时钟提供给 缓冲存储器，通过在恢复写入时钟供应之后的预定时间经过接收帧位置指定脉冲。 写入缓冲存储器的数据可以在期望的帧相位和数据速度读出，而不会复制和丢失读取的数据。
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公开(公告)号：US4048447A
公开(公告)日：1977-09-13
申请号：US688243
申请日：1976-05-20
申请人： Rikio Maruta
发明人： Rikio Maruta
CPC分类号： H04J3/172
摘要： A PCM-TASI signal transmission system utilizes assignment control means responsive to an output signal from means for detecting the presence of information on each of a plurality (m) of input trunks arranged in time-serial fashion. The assignment control means selectively assigns a PCM signal representing the input trunk signal, during the period when information is present thereon, to one of a second plurality (s) of transmission channels (s
摘要翻译： PCM-TASI信号传输系统利用分配控制装置，响应来自用于检测以时间序列方式排列的多（m）个输入干线中的每一个上的信息的存在的装置的输出信号。 分配控制装置在信息存在的时段期间选择性地分配表示输入的中继线信号的PCM信号到第二多个传输信道（s
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公开(公告)号：US4935921A
公开(公告)日：1990-06-19
申请号：US99963
申请日：1987-09-23
摘要： In a cross-connection network, a plurality of asynchronous input digital signals can be cross-connected to a plurality of output lines by use of time switch. The input digital signals are pulse stuffed at a common higher bit rate and are synchronized to one another by attaching extra bits. The pulse stuffed signals are assigned into serial frames in a predetermined order by the multiplex technique and are interchanged from one to another by the time switch in the time division fashion. The frame-interchanged signal is demultiplexed to reproduce the pulse-stuffed signals which are sent out to the respective output lines assigned to the frames after removing extra bits. When the input digital signals are of higher order group, each of the higher order group digital signals is demultiplexed to lower order group signals which are pulse stuffed to be synchronized to the common higher bit rate. The pulse stuffed lower order signals are rearranged by the multiplex technique to reform each of the high order group signal which is synchronized to one another. The reformed higher order group signals are assigned in serial frames and are processed in the similar manner as described above. The frame-interchanged signals are reversely processed to be separated, demultiplexed, destuffed, and multiplexed to reproduce the input signals as the output signals.
摘要翻译： 在交叉连接网络中，多个异步输入数字信号可以通过使用时间切换与多个输出线交叉连接。 输入的数字信号以相同的较高比特率脉冲填充，并通过附加额外的比特来彼此同步。 脉冲填充信号通过多路复用技术以预定顺序被分配给串行帧，并且通过时分方式以时分交换方式从一个到另一个互换。 帧互换信号被解复用以再现脉冲填充信号，该脉冲填充信号在去除额外位之后发送到分配给帧的相应输出线。 当输入数字信号为高阶组时，高阶组数字信号中的每一个被解复用为脉冲填充的较低阶组信号以与公共较高比特率同步。 脉冲填充的低阶信号通过多路技术重新排列，以重新形成彼此同步的高阶组信号。 改进的高阶组信号以串行帧分配，并以与上述相似的方式进行处理。 帧互换的信号被反向处理以被分离，解复用，解消融和多路复用以再现作为输出信号的输入信号。
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公开(公告)号：US4393367A
公开(公告)日：1983-07-12
申请号：US69384
申请日：1979-08-24
申请人： Rikio Maruta , Atsushi Tomozawa
发明人： Rikio Maruta , Atsushi Tomozawa
摘要： A compandor converts a linear code signal consisting of a polarity bit and a plurality of absolute value bits. The polarity bit represents the polarity of each sample value of an original analog signal. The absolute value bits represent the absolute value of the sample. The compandor converts the linear code into a nonlinear code including the polarity bit, a plurality of segment bits representing the segments in a characteristic curve to which the original analog signal belongs, and mantissa bits which indicate the position of the sample value in that segment. The compandor comprises: a plurality of input terminals for receiving the linear code signal; a first read-only memory means, addressed by a first bit group among the absolute value bits for memorizing a segment bit decision rule; a second read-only memory means, addressed by a second bit group consisting of another plurality of bits among the absolute value bits and some bits in common with the first bit group for memorizing a first mantissa bit decision rule; a third read-only memory means, addressed by the first bit group, for memorizing a second mantissa bit decision rule; and means for selecting the second or third read-only memory means depending on the value of the most significant bit among the segment bits supplied from the first read-only memory means.
摘要翻译： 压缩器转换由极性位和多个绝对值位组成的线性码信号。 极性位表示原始模拟信号的每个采样值的极性。 绝对值位代表样本的绝对值。 压缩器将线性代码转换为非线性代码，其包括极性位，表示原始模拟信号所属的特性曲线中的段的多个段位以及指示该段中的采样值的位置的尾数位。 该压缩器包括：用于接收线性码信号的多个输入端; 第一只读存储器装置，用于存储段位决定规则的绝对值位之中的第一位组寻址; 第二只读存储器装置，由绝对值位中的另外多个位组成的第二位组寻址，以及与用于存储第一尾数位决定规则的第一位组共同的一些位; 由第一位组寻址的用于存储第二尾数位决定规则的第三只读存储器装置; 以及用于根据从第一只读存储器装置提供的段位中的最高有效位的值来选择第二或第三只读存储器装置的装置。
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10.发明授权Method and apparatus for converting an analog signal to a digital signal using an oversampling technique 失效使用过采样技术将模拟信号转换为数字信号的方法和装置
公开(公告)号：US4684925A
公开(公告)日：1987-08-04
申请号：US751909
申请日：1985-07-05
申请人： Rikio Maruta
发明人： Rikio Maruta
摘要： An A-D converter which oversamples the input analog signal, at a frequency greater than the Nyquist frequency, and achieves high precision linear coding by performing simple operations at a high sampling frequency f.sub.H while complicated operations are performed at a low sampling frequency f.sub.s. The high sampling frequency may be reduced to the low sampling frequency through a two-step reduction using a sampling frequency converter to reduce the frequency to an intermediate frequency f.sub.M and an integrator/sampler to reduce the sampling frequency further to f.sub.s or directly with the use of an FIR filter having a frequency characteristic in which attenuation is large in the out-of-band and gain deviation is small in-band.
摘要翻译： A-D转换器以大于奈奎斯特频率的频率对输入模拟信号进行过采样，并通过以较低的采样频率fs进行复杂的操作，以高采样频率fH进行简单的操作，实现高精度的线性编码。 通过使用采样频率转换器的两级降低可以将高采样频率降低到低采样频率，以将频率降低到中频fM和积分器/采样器，以将采样频率进一步降低至fs或直接使用 具有带外衰减大的频率特性的FIR滤波器和增益偏差小的带内。
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