公开(公告)号：US08037377B1

公开(公告)日：2011-10-11

申请号：US12127783

申请日：2008-05-27

申请人： Ie Chen Chia ,  Eng Huat Lee ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

发明人： Ie Chen Chia ,  Eng Huat Lee ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

IPC分类号： G01R31/28

CPC分类号： G01R31/31716

摘要： A circuit includes a receiver channel and a built-in self-test circuit. The receiver channel has a serializer and a deserializer. The built-in self-test circuit generates test signals that are transmitted in parallel to the serializer during a test of the receiver channel. The serializer converts the test signals into serial test signals. The deserializer converts the serial test signals into parallel test signals that are transmitted to the built-in self-test circuit.

摘要翻译： 电路包括接收器通道和内置自检电路。 接收器通道具有串行器和解串器。 内置的自检电路在接收机通道测试期间产生并行发送到串行器的测试信号。 串行器将测试信号转换为串行测试信号。 解串器将串行测试信号转换为并行测试信号，传输到内置的自检电路。

公开(公告)号：US08659334B2

公开(公告)日：2014-02-25

申请号：US13543724

申请日：2012-07-06

申请人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

发明人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  G11C17/16 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402 ,  H03L7/08

摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。 所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。 控制块读取存储在可编程保险丝中的设置或数据。 耦合到控制块的调谐电路接收由控制块发送的延迟。 调谐电路允许调节IC而不改变制造掩模。 调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

公开(公告)号：US20120274375A1

公开(公告)日：2012-11-01

申请号：US13543724

申请日：2012-07-06

申请人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

发明人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

IPC分类号： H03K3/86 ,  H03L7/06

CPC分类号： H03L7/081 ,  G11C17/16 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402 ,  H03L7/08

摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。 所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。 控制块读取存储在可编程保险丝中的设置或数据。 耦合到控制块的调谐电路接收由控制块发送的延迟。 调谐电路允许调节IC而不改变制造掩模。 调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

公开(公告)号：US08232823B1

公开(公告)日：2012-07-31

申请号：US12479515

申请日：2009-06-05

申请人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

发明人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  G11C17/16 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402 ,  H03L7/08

摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。 所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。 控制块读取存储在可编程保险丝中的设置或数据。 耦合到控制块的调谐电路接收由控制块发送的延迟。 调谐电路允许调节IC而不改变制造掩模。 调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

公开(公告)号：US07639047B1

公开(公告)日：2009-12-29

申请号：US12053573

申请日：2008-03-22

申请人： Boon Jin Ang ,  Bee Yee Ng ,  Eng Huat Lee ,  Thow Pang Chong ,  Teng Kuan Koay

发明人： Boon Jin Ang ,  Bee Yee Ng ,  Eng Huat Lee ,  Thow Pang Chong ,  Teng Kuan Koay

IPC分类号： H03K19/00

CPC分类号： G06F1/10

摘要： A circuit includes a clock routing network. The clock routing network includes first and second clock paths. The first clock path routes a first clock signal to sub-circuits in the circuit. The first clock path has first buffers that buffer the first clock signal at the sub-circuits and first conductors in a first conductive layer of the circuit that transmit the first clock signal. The second clock path routes a second clock signal to the sub-circuits. The second clock path has second buffers that buffer the second clock signal at the sub-circuits, second conductors in the first conductive layer that transmit the second clock signal, and third conductors in a second conductive layer of the circuit. The second clock signal is routed through the third conductors at overlaps between the first clock path and the second clock path.

摘要翻译： 电路包括时钟路由网络。 时钟路由网络包括第一和第二时钟路径。 第一时钟路径将第一时钟信号路由到电路中的子电路。 第一时钟路径具有缓冲第一时钟信号在子电路处的第一缓冲器和传输第一时钟信号的电路的第一导电层中的第一导体。 第二时钟路径将第二时钟信号路由到子电路。 第二时钟路径具有缓冲子电路上的第二时钟信号的第二缓冲器，传输第二时钟信号的第一导电层中的第二导体和在该电路的第二导电层中的第三导体。 第二时钟信号在第一时钟路径和第二时钟路径之间的重叠处被路由穿过第三导体。

公开(公告)号：US08120407B1

公开(公告)日：2012-02-21

申请号：US12642738

申请日：2009-12-18

申请人： Teng Chow Ooi ,  Eng Huat Lee ,  Chuan Khye Chai ,  Yew Fatt (Edwin) Kok ,  Sergey Shumarayev

发明人： Teng Chow Ooi ,  Eng Huat Lee ,  Chuan Khye Chai ,  Yew Fatt (Edwin) Kok ,  Sergey Shumarayev

IPC分类号： H03K23/00

CPC分类号： H03K5/135 ,  H03K2005/00286

摘要： A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal in first and second directions when the gain signal has a first value. The phase change circuit increases phase shifts provided to the first periodic signal in the first direction in response to the gain signal changing from the first value to a second value. The phase change circuit provides phase shifts to the first periodic signal in the second direction when the gain signal has the second value that are smaller than the phase shifts provided to the first periodic signal in the first direction when the gain signal has the second value.

摘要翻译： 电路包括相位检测电路和相变电路。 相位检测电路将第一周期性信号的相位与输入信号进行比较，以产生增益信号。 当增益信号具有第一值时，相变电路在第一和第二方向上向第一周期性信号提供相移。 响应于增益信号从第一值改变到第二值，相变电路增加提供给第一周期信号的第一方向的相移。 当增益信号具有小于当增益信号具有第二值时在第一方向上提供给第一周期信号的相移的第二值时，相变电路在第二方向上向第一周期信号提供相移。