公开(公告)号：US20120274375A1

公开(公告)日：2012-11-01

申请号：US13543724

申请日：2012-07-06

申请人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

发明人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

IPC分类号： H03K3/86 ,  H03L7/06

CPC分类号： H03L7/081 ,  G11C17/16 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402 ,  H03L7/08

摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。 所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。 控制块读取存储在可编程保险丝中的设置或数据。 耦合到控制块的调谐电路接收由控制块发送的延迟。 调谐电路允许调节IC而不改变制造掩模。 调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

公开(公告)号：US08232823B1

公开(公告)日：2012-07-31

申请号：US12479515

申请日：2009-06-05

申请人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

发明人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  G11C17/16 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402 ,  H03L7/08

摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。 所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。 控制块读取存储在可编程保险丝中的设置或数据。 耦合到控制块的调谐电路接收由控制块发送的延迟。 调谐电路允许调节IC而不改变制造掩模。 调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

公开(公告)号：US08659334B2

公开(公告)日：2014-02-25

申请号：US13543724

申请日：2012-07-06

申请人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

发明人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  G11C17/16 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402 ,  H03L7/08

摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。 所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。 控制块读取存储在可编程保险丝中的设置或数据。 耦合到控制块的调谐电路接收由控制块发送的延迟。 调谐电路允许调节IC而不改变制造掩模。 调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

公开(公告)号：US20240126228A1

公开(公告)日：2024-04-18

申请号：US18398709

申请日：2023-12-28

申请人： Archanna Srinivasan ,  Teik Wah Lim ,  Pravin Chander Chandran

发明人： Archanna Srinivasan ,  Teik Wah Lim ,  Pravin Chander Chandran

IPC分类号： G05B19/05

CPC分类号： G05B19/056 ,  G05B2219/13004

摘要： Systems or methods of the present disclosure may provide for implementing design software that is used to design a configuration for a programmable fabric of a programmable logic device. Implementing the design software includes receiving, at a processor, design configuration details for the configuration. Implementing the design software also includes receiving, at the processor, a plurality of constraints including a thermal constraint for the configuration. Moreover, implementing the design software comprises performing thermal aware resource selection based at least in part on the thermal constraint. Furthermore, implementing the design software includes causing the programmable logic device to be operated to stay within the thermal constraint.

公开(公告)号：US08327305B1

公开(公告)日：2012-12-04

申请号：US12534053

申请日：2009-07-31

申请人： Woi Jie Hooi ,  Teik Wah Lim ,  Ket Chiew Sia

发明人： Woi Jie Hooi ,  Teik Wah Lim ,  Ket Chiew Sia

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A circuit and methods for placing a circuit block on an integrated circuit (IC) are disclosed. An embodiment of the disclosed method includes dividing the IC into multiple regions based on pre-determined value. This pre-determined value may be a voltage drop value measured on specific regions on the IC. The performance requirement for the circuit block is determined and placed in one of the regions on the IC. In one embodiment, the placement of the circuit block is based on the performance requirement and the measured value at specific regions on the IC. The measured value may be a voltage drop value and a circuit block with a higher performance may be placed in a region with a lower voltage drop value.

摘要翻译： 公开了一种将电路块放置在集成电路（IC）上的电路和方法。 所公开方法的实施例包括基于预定值将IC划分成多个区域。 该预定值可以是在IC上的特定区域上测量的电压降值。 电路块的性能要求被确定并放置在IC的一个区域中。 在一个实施例中，电路块的放置基于IC上的特定区域的性能要求和测量值。 测量值可以是电压降值，并且具有较高性能的电路块可以放置在具有较低电压降值的区域中。