公开(公告)号：US20190215156A1

公开(公告)日：2019-07-11

申请号：US16242003

申请日：2019-01-08

Applicant: Infineon Technologies AG

Inventor： Berndt GAMMEL ,  Bernd MEYER

IPC: H04L9/08 ,  G06F21/60

CPC classification number: H04L9/0861 ,  G06F21/602

Abstract: A chip includes a processing device to perform cryptographic operations by secret data; a memory to store a first plurality of information portions that correspond to a first breakdown of the data and from which the secret data are reconstructible by combination of the first plurality of information portions; a random number generator to provide random values; and a conversion device to ascertain second breakdowns of the data into a second plurality of information portions, from which the secret data are reconstructible and to control the memory for an ascertained second breakdown to store the present second plurality of information portions. The conversion device is further configured to ascertain the second breakdowns based on the random values and/or to determine the interval of time between the ascertaining and storing of a second breakdown and the ascertaining and storing of the subsequent second breakdown based on the random values.

公开(公告)号：US20180091149A1

公开(公告)日：2018-03-29

申请号：US15718033

申请日：2017-09-28

Applicant: Infineon Technologies AG

Inventor： Thomas KUENEMUND ,  Molka BEN ROMDHANE ,  Berndt GAMMEL

IPC: H03K19/007 ,  H03K3/3562

CPC classification number: H03K19/007 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/3562

Abstract: According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.

公开(公告)号：US20130318327A1

公开(公告)日：2013-11-28

申请号：US13899655

申请日：2013-05-22

Applicant: Infineon Technologies AG

Inventor： Berndt GAMMEL ,  Stefan MANGARD

IPC: G06F9/30

CPC classification number: G06F9/30 ,  G06F9/30076 ,  G06F9/30145 ,  G06F11/0763

Abstract: A method for processing an operating sequence of instructions of a program in a processor, wherein each instruction is represented by an assigned instruction code which comprises one execution step to be processed by the processor or a plurality of execution steps to be processed successively by the processor, includes determining an actual signature value assigned to a current execution step of the execution steps of the instruction code representing the instruction of the operating sequence; determining, in a manner dependent on an address value, a desired signature value assigned to the current execution step; and if the actual signature value does not correspond to the desired signature value, omitting at least one execution step directly available for execution and/or an execution step indirectly available for execution.

公开(公告)号：US20170116437A1

公开(公告)日：2017-04-27

申请号：US15333205

申请日：2016-10-25

Applicant: Infineon Technologies AG

Inventor： Berndt GAMMEL ,  Stefan HEISS ,  Markus RAU

IPC: G06F21/64 ,  G06F21/62

CPC classification number: G06F21/556 ,  H04L9/003 ,  H04L9/0894 ,  H04L2209/046

Abstract: According to one embodiment, a method for protecting data is provided comprising receiving a plurality of data symbols, determining a sequence of checksum symbols wherein the checksum symbols are determined to be equal to the checksum symbols of the last iteration of an iterative checksum symbol generation process, wherein the determining of the checksum symbols includes at least one of randomly generating the initial values, randomly determining an order of the data symbols in which the contributions of the data symbols to the checksum symbols are incorporated into the checksum symbols and masking each data symbol and using the masked data symbols as data symbols for determining the checksum symbols and which includes storing at least some of the checksum values as checksum for the data symbols.

公开(公告)号：US20150331810A1

公开(公告)日：2015-11-19

申请号：US14280823

申请日：2014-05-19

Applicant: Infineon Technologies AG

Inventor： Berndt GAMMEL ,  Tomaz FELICIJAN ,  Stefan MANGARD ,  Walter MERGLER

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F12/145 ,  G06F21/75 ,  G06F21/755 ,  G06F2212/1052 ,  G06F2212/251

Abstract: An embodiment relates to a device for a memory access, the device comprising a first component for conducting operations on the memory and a second component for accessing the memory in a randomized manner, wherein the first component conducts at least a portion of the operations via the second component.

Abstract translation: 一个实施例涉及一种用于存储器访问的设备，该设备包括用于在存储器上进行操作的第一组件和用于以随机方式访问存储器的第二组件，其中第一组件通过以下操作进行至少一部分操作： 第二部分。

公开(公告)号：US20210019417A1

公开(公告)日：2021-01-21

申请号：US16515633

申请日：2019-07-18

Applicant: Infineon Technologies AG

Inventor： Alexander ZEH ,  Veit KLEEBERGER ,  Berndt GAMMEL

IPC: G06F21/57 ,  G06F21/62 ,  G06F21/79

Abstract: A hybrid device includes a plurality of diverse subsystems, including a first and a second subsystem. The first subsystem includes at least one first secured storage device configured to store a first software and a first CPU configured to boot and execute the first software. The second subsystem includes at least one second secured storage device configured to store a second software and a second CPU configured to boot and execute the second software. The first CPU is configured to generate the first hash of the first software and transmit the generated first hash of the first software to the second subsystem. The second CPU is configured to perform a first authenticity validation check on the first software using the received first hash of the first software, and generate an error signal on a condition that the first authenticity validation check on the first software fails.

公开(公告)号：US20150144697A1

公开(公告)日：2015-05-28

申请号：US14549578

申请日：2014-11-21

Applicant: Infineon Technologies AG

Inventor： Martin KLIMKE ,  Berndt GAMMEL ,  Frank PUESCHNER ,  Peter STAMPKA

IPC: G06K7/12

CPC classification number: G06K19/07381 ,  G06K19/06009 ,  G06K19/077

Abstract: One embodiment describes a chip arrangement having a chip carrier; a chip which is arranged in or on the chip carrier; a light sensor arrangement; a transparent layer which covers the light sensor arrangement, the light sensor arrangement being set up to determine a light pattern of light received by the light sensor arrangement from outside the chip arrangement through the transparent layer; and a test circuit which is set up to check whether the light pattern matches a reference light pattern and to output a signal on the basis of the result of the check.

Abstract translation: 一个实施例描述了具有芯片载体的芯片布置; 布置在芯片载体上或芯片载体上的芯片; 光传感器装置; 覆盖所述光传感器装置的透明层，所述光传感器装置被设置为通过所述透明层从所述芯片布置的外部确定由所述光传感器装置接收的光的光图案; 以及测试电路，其被设置为检查光图案是否与参考光图案匹配并且基于检查结果输出信号。

公开(公告)号：US20150067012A1

公开(公告)日：2015-03-05

申请号：US14470953

申请日：2014-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Rainer GOETTFERT ,  Berndt GAMMEL ,  Thomas KUENEMUND

IPC: G06F17/16

CPC classification number: G06F17/16 ,  G06F7/588 ,  H04L9/0866 ,  H04L2209/34

Abstract: A method for reconstructing a first vector from a second vector includes: storing code for the row vectors according to a first code and a second code; correcting the row vectors of the second vector corresponding to the first vector so that the row vectors of the second vector have the same code as the row vectors of the first vector; calculating the code of the column vectors of the second vector according to the second code; comparing the code of the row vectors of the second vector with the code of the column vectors of the first vector; identifying the columns in which the first vector is unequal to the second vector; the rows in which the first vector is unequal to the second vector; and the components in which the first vector is not equal to the second vector, and correcting the components of the second vector.

Abstract translation: 一种从第二矢量重构第一矢量的方法包括：根据第一码和第二码存储行向量的码; 对与第一向量相对应的第二向量的行向量进行校正，使得第二向量的行向量具有与第一向量的行向量相同的代码; 根据第二代码计算第二向量的列向量的代码; 将第二向量的行向量的代码与第一向量的列向量的代码进行比较; 识别第一个向量不等于第二个向量的列; 第一个向量不等于第二个向量的行; 以及其中第一矢量不等于第二矢量的分量，以及校正第二矢量的分量。