公开(公告)号：US20170040425A1

公开(公告)日：2017-02-09

申请号：US15221122

申请日：2016-07-27

Applicant: Infineon Technologies AG

Inventor： Daniel KUECK ,  Thomas AICHINGER ,  Franz HIRLER ,  Anton MAUDER

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a source zone electrically connected to a first load terminal, a contiguous zone isolating the source zone from a drift zone, and a trench extending into a semiconductor body along a vertical direction and including a first electrode electrically connected to a control terminal and an insulator in contact with the contiguous zone and which isolates the first electrode from the semiconductor body. The insulator has, at a trench bottom region, a first thickness along the vertical direction, and, at a trench top region, a second thickness along a lateral direction, the first thickness being greater than the second thickness by a factor of at least 1.5. The contiguous zone is arranged in contact with the insulator and extends further along the vertical direction than the trench, and the trench bottom region and the contiguous zone overlap along the lateral direction.

Abstract translation: 半导体器件包括电连接到第一负载端子的源极区域，将源区域与漂移区隔离的连续区域以及沿着垂直方向延伸到半导体本体中的沟槽，并且包括电连接到控制端子的第一电极 以及与所述连续区域接触并将所述第一电极与所述半导体本体隔离的绝缘体。 绝缘体在沟槽底部区域沿着垂直方向具有第一厚度，并且在沟槽顶部区域处沿着横向方向具有第二厚度，第一厚度大于第二厚度至少为1.5倍 。 连续区域布置成与绝缘体接触并且沿着垂直方向进一步沿着沟槽延伸，并且沟槽底部区域和连续区域沿着横向方向重叠。

公开(公告)号：US20200006544A1

公开(公告)日：2020-01-02

申请号：US16454752

申请日：2019-06-27

Applicant: Infineon Technologies AG

Inventor： Ralf SIEMIENIEC ,  Thomas AICHINGER ,  Wolfgang BERGNER ,  Romain ESTEVE ,  Daniel KUECK ,  Dethard PETERS ,  Bernd ZIPPELIUS

IPC: H01L29/78 ,  H01L29/16

Abstract: A semiconductor device includes a silicon carbide body including a transistor cell region and an idle region. The transistor cell region includes transistor cells. The idle region is devoid of transistor cells. The idle region includes a transition region between the transistor cell region and a side surface of the silicon carbide body, a gate pad region, and a diode structure comprising at least one of a merged pin Schottky diode structure or a merged pin heterojunction diode structure in at least one of the transition region or the gate pad region.