公开(公告)号：US20170040425A1

公开(公告)日：2017-02-09

申请号：US15221122

申请日：2016-07-27

Applicant: Infineon Technologies AG

Inventor： Daniel KUECK ,  Thomas AICHINGER ,  Franz HIRLER ,  Anton MAUDER

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a source zone electrically connected to a first load terminal, a contiguous zone isolating the source zone from a drift zone, and a trench extending into a semiconductor body along a vertical direction and including a first electrode electrically connected to a control terminal and an insulator in contact with the contiguous zone and which isolates the first electrode from the semiconductor body. The insulator has, at a trench bottom region, a first thickness along the vertical direction, and, at a trench top region, a second thickness along a lateral direction, the first thickness being greater than the second thickness by a factor of at least 1.5. The contiguous zone is arranged in contact with the insulator and extends further along the vertical direction than the trench, and the trench bottom region and the contiguous zone overlap along the lateral direction.

Abstract translation: 半导体器件包括电连接到第一负载端子的源极区域，将源区域与漂移区隔离的连续区域以及沿着垂直方向延伸到半导体本体中的沟槽，并且包括电连接到控制端子的第一电极 以及与所述连续区域接触并将所述第一电极与所述半导体本体隔离的绝缘体。 绝缘体在沟槽底部区域沿着垂直方向具有第一厚度，并且在沟槽顶部区域处沿着横向方向具有第二厚度，第一厚度大于第二厚度至少为1.5倍 。 连续区域布置成与绝缘体接触并且沿着垂直方向进一步沿着沟槽延伸，并且沟槽底部区域和连续区域沿着横向方向重叠。

公开(公告)号：US20180175150A1

公开(公告)日：2018-06-21

申请号：US15848707

申请日：2017-12-20

Applicant: Infineon Technologies AG

Inventor： Anton MAUDER ,  Oliver HELLMUND ,  Peter IRSIGLER ,  Jens Peter KONRATH ,  David LAFORET ,  Maik LANGNER ,  Markus NEUBER ,  Hans-Joachim SCHULZE ,  Ralf SIEMIENIEC ,  Knut STAHRENBERG ,  Olaf STORBECK

IPC: H01L29/16 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02

Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.

公开(公告)号：US20230223472A1

公开(公告)日：2023-07-13

申请号：US18152550

申请日：2023-01-10

Applicant: Infineon Technologies AG

Inventor： Anton MAUDER ,  Stefano RUZZA ,  Massimo GRASSO ,  Richard KUCHCINSKI ,  Daniel DOMES

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7815 ,  H01L29/0696

Abstract: A semiconductor assembly includes a semiconductor switching device, a conductive load base structure, and a current sense unit. The semiconductor switching device includes a drain structure and one or more array units, wherein each array unit includes a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure. The current sense unit is electrically connected between a first one of the load pads and the load base structure.

公开(公告)号：US20160035665A1

公开(公告)日：2016-02-04

申请号：US14450300

申请日：2014-08-04

Applicant: Infineon Technologies AG

Inventor： Ralf OTREMBA ,  Klaus SCHIESS ,  Anton MAUDER

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49844 ,  H01L23/3114 ,  H01L23/3121 ,  H01L25/072 ,  H01L2924/0002 ,  H02M1/088 ,  H01L2924/00

Abstract: A circuit arrangement is provided, which may include: an embedding package chip carrier; a first chip and a second chip arranged over the embedding package chip carrier, each of the first chip and the second chip comprising: a control terminal, a first controlled terminal, and a second controlled terminal, wherein the control terminal and the first controlled terminal are arranged on a first side of the chip, and wherein the second controlled terminal is arranged on a second side of the chip, wherein the second side is opposite the first side; wherein the first chip is arranged on the embedding package chip carrier such that its first side is facing towards the embedding package chip carrier; and wherein the second chip is arranged on the embedding package chip carrier such that its first side is facing away from the embedding package chip carrier.

Abstract translation: 提供一种电路装置，其可包括：嵌入式封装芯片载体; 布置在所述嵌入式封装芯片载体上的第一芯片和第二芯片，所述第一芯片和所述第二芯片中的每一个包括：控制端子，第一受控端子和第二受控端子，其中所述控制端子和所述第一受控端子 布置在所述芯片的第一侧上，并且其中所述第二受控端子布置在所述芯片的第二侧上，其中所述第二侧与所述第一侧相对; 其中所述第一芯片布置在所述嵌入式封装芯片载体上，使得其第一侧面向所述嵌入封装芯片载体; 并且其中所述第二芯片布置在所述嵌入式封装芯片载体上，使得其第一侧面朝向远离所述嵌入封装芯片载体。

公开(公告)号：US20130069065A1

公开(公告)日：2013-03-21

申请号：US13621834

申请日：2012-09-17

Applicant: Infineon Technologies AG

Inventor： Anton MAUDER ,  Roland RUPP ,  Hans-Joachim SCHULZE

IPC: H01L29/04 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66068 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/402 ,  H01L29/408 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device may include a semiconductor body of silicon carbide (SiC) and a field effect transistor. The field effect transistor has the semiconductor body that includes a drift region. A polycrystalline silicon layer is formed over or on the semiconductor body, wherein the polycrystalline silicon layer has an average particle size in the range of 10 nm to 5 μm, and includes a source region and a body region. Furthermore, the field effect transistor includes a layer adjacent to the body region gate structure.

Abstract translation: 半导体器件可以包括碳化硅（SiC）的半导体本体和场效应晶体管。 场效应晶体管具有包括漂移区域的半导体本体。 多晶硅层形成在半导体本体的上方或之上，其中多晶硅层的平均粒径在10nm至5μm的范围内，并且包括源极区域和体区域。 此外，场效应晶体管包括与体区域栅极结构相邻的层。

公开(公告)号：US20140306327A1

公开(公告)日：2014-10-16

申请号：US13862398

申请日：2013-04-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Hans-Joachim SCHULZE ,  Johannes BAUMGARTL ,  Gerald LACKNER ,  Anton MAUDER ,  Francisco Javier SANTOS RODRIGUEZ

IPC: H01L21/52 ,  H01L23/053 ,  H01L21/78 ,  H01L23/043

CPC classification number: H01L21/52 ,  H01L21/50 ,  H01L21/78 ,  H01L23/04 ,  H01L23/043 ,  H01L23/053 ,  H01L24/11 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00

Abstract: A semiconductor device includes a device carrier and a semiconductor chip attached to the device carrier. Further, the semiconductor device includes a lid having a recess. The lid includes a semiconductor material and is attached to the device carrier such that the semiconductor chip is accommodated in the recess.

Abstract translation: 半导体器件包括器件载体和附着于器件载体的半导体芯片。 此外，半导体器件包括具有凹部的盖。 盖子包括一个半导体材料，并附着在器件载体上，使半导体芯片容纳在凹槽中。