公开(公告)号：US20210119006A1

公开(公告)日：2021-04-22

申请号：US17072602

申请日：2020-10-16

Applicant: Infineon Technologies AG

Inventor： Thomas AICHINGER ,  Wolfgang BERGNER ,  Ralf SIEMIENIEC ,  Frank WOLTER

IPC: H01L29/43 ,  H01L29/10 ,  H01L29/423 ,  H01L29/16

Abstract: In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.

公开(公告)号：US20220262906A1

公开(公告)日：2022-08-18

申请号：US17671838

申请日：2022-02-15

Applicant: Infineon Technologies AG

Inventor： Ralf SIEMIENIEC ,  Thomas AICHINGER ,  Ravi Keshav JOSHI ,  Werner SCHUSTEREDER

IPC: H01L29/16 ,  H01L29/423 ,  H01L21/04 ,  H01L29/78 ,  H01L29/66

Abstract: A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for forming a SiC MOSFET are disclosed. In an example, the method includes forming a gate dielectric that adjoins a body region arranged in a semiconductor body, and forming a gate electrode on the gate dielectric. Forming the gate electrode includes forming a first electrode layer, implanting work function adjusting atoms into the first electrode layer, and forming a second electrode layer on the first electrode layer.

公开(公告)号：US20200006544A1

公开(公告)日：2020-01-02

申请号：US16454752

申请日：2019-06-27

Applicant: Infineon Technologies AG

Inventor： Ralf SIEMIENIEC ,  Thomas AICHINGER ,  Wolfgang BERGNER ,  Romain ESTEVE ,  Daniel KUECK ,  Dethard PETERS ,  Bernd ZIPPELIUS

IPC: H01L29/78 ,  H01L29/16

Abstract: A semiconductor device includes a silicon carbide body including a transistor cell region and an idle region. The transistor cell region includes transistor cells. The idle region is devoid of transistor cells. The idle region includes a transition region between the transistor cell region and a side surface of the silicon carbide body, a gate pad region, and a diode structure comprising at least one of a merged pin Schottky diode structure or a merged pin heterojunction diode structure in at least one of the transition region or the gate pad region.

公开(公告)号：US20240222498A1

公开(公告)日：2024-07-04

申请号：US18605438

申请日：2024-03-14

Applicant: Infineon Technologies AG

Inventor： Ralf SIEMIENIEC ,  Wolfgang JANTSCHER ,  David KAMMERLANDER

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/1608 ,  H01L29/66734

Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

公开(公告)号：US20230024105A1

公开(公告)日：2023-01-26

申请号：US17869567

申请日：2022-07-20

Applicant: Infineon Technologies AG

Inventor： Werner SCHUSTEREDER ,  Ravi Keshav JOSHI ,  Hans-Joachim SCHULZE ,  Ralf SIEMIENIEC ,  Axel KOENIG

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45

Abstract: The present disclosure relates to methods of manufacturing Ohmic contacts on a silicon carbide (SiC) substrate including providing a 4H—SiC or 6H—SiC substrate, implanting dopants into a surface region of the 4H—SiC or 6H—SiC substrate, annealing the implanted surface regions to form a 3C—SiC layer, and depositing a metal layer on the 3C—SiC layer. An implanting sequence of the implantation of dopants includes a plurality of plasma deposition acts with implantation energy levels including at least two different implantation energy levels. The implantation energy levels and one or more implantation doses of the plurality of plasma deposition acts are selected to form a 3C—SiC layer in the surface region of the 4H—SiC or 6H—SiC substrate during the annealing act. A method of manufacturing a semiconductor device having a structure including at least three layers including a 4H—SiC or 6H—SiC layer, a 3C—SiC layer, and a metal layer, by applying one or more of the techniques described herein, and semiconductor devices obtained with one or more of the techniques described herein are described.

公开(公告)号：US20180175150A1

公开(公告)日：2018-06-21

申请号：US15848707

申请日：2017-12-20

Applicant: Infineon Technologies AG

Inventor： Anton MAUDER ,  Oliver HELLMUND ,  Peter IRSIGLER ,  Jens Peter KONRATH ,  David LAFORET ,  Maik LANGNER ,  Markus NEUBER ,  Hans-Joachim SCHULZE ,  Ralf SIEMIENIEC ,  Knut STAHRENBERG ,  Olaf STORBECK

IPC: H01L29/16 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02

Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.