公开(公告)号：US20220262906A1

公开(公告)日：2022-08-18

申请号：US17671838

申请日：2022-02-15

Applicant: Infineon Technologies AG

Inventor： Ralf SIEMIENIEC ,  Thomas AICHINGER ,  Ravi Keshav JOSHI ,  Werner SCHUSTEREDER

IPC: H01L29/16 ,  H01L29/423 ,  H01L21/04 ,  H01L29/78 ,  H01L29/66

Abstract: A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for forming a SiC MOSFET are disclosed. In an example, the method includes forming a gate dielectric that adjoins a body region arranged in a semiconductor body, and forming a gate electrode on the gate dielectric. Forming the gate electrode includes forming a first electrode layer, implanting work function adjusting atoms into the first electrode layer, and forming a second electrode layer on the first electrode layer.

公开(公告)号：US20250089343A1

公开(公告)日：2025-03-13

申请号：US18824073

申请日：2024-09-04

Applicant: Infineon Technologies AG

Inventor： Andreas HÜRNER ,  Michael HELL ,  Thomas AICHINGER

IPC: H01L29/51 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A power semiconductor device is proposed. The power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising transistor cells. Each of the transistor cells includes a gate structure including a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure includes a first gate dielectric layer adjoining to the SiC semiconductor body. The gate dielectric structure further includes a second gate dielectric layer. The gate dielectric structure further includes charge storage layer arranged between the first gate dielectric layer and the second gate dielectric layer.

公开(公告)号：US20200006544A1

公开(公告)日：2020-01-02

申请号：US16454752

申请日：2019-06-27

Applicant: Infineon Technologies AG

Inventor： Ralf SIEMIENIEC ,  Thomas AICHINGER ,  Wolfgang BERGNER ,  Romain ESTEVE ,  Daniel KUECK ,  Dethard PETERS ,  Bernd ZIPPELIUS

IPC: H01L29/78 ,  H01L29/16

Abstract: A semiconductor device includes a silicon carbide body including a transistor cell region and an idle region. The transistor cell region includes transistor cells. The idle region is devoid of transistor cells. The idle region includes a transition region between the transistor cell region and a side surface of the silicon carbide body, a gate pad region, and a diode structure comprising at least one of a merged pin Schottky diode structure or a merged pin heterojunction diode structure in at least one of the transition region or the gate pad region.

公开(公告)号：US20250056869A1

公开(公告)日：2025-02-13

申请号：US18799436

申请日：2024-08-09

Applicant: Infineon Technologies AG

Inventor： Fabian RASINGER ,  Michael HELL ,  Thomas AICHINGER ,  Alexey MIKHAYLOV

IPC: H01L29/51 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/423

Abstract: A wide band gap semiconductor device is proposed. The wide band gap semiconductor device includes a wide band gap semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction. A gate electrode structure is arranged in an active transistor area. The gate electrode structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the wide band gap semiconductor body. A gate interconnection structure is arranged outside of the active transistor area. The gate interconnection structure includes an interconnection electrode and an interconnection dielectric arranged between the interconnection electrode and the wide band gap semiconductor body. Dielectric constants of a main dielectric component of at least two of i) a part of the gate interconnection dielectric, or ii) a first part of the gate dielectric, or iii) a second part of the gate dielectric differ from one another.

公开(公告)号：US20250006814A1

公开(公告)日：2025-01-02

申请号：US18756389

申请日：2024-06-27

Applicant: Infineon Technologies AG

Inventor： Wolfgang LEHNERT ,  Fabian RASINGER ,  Thomas AICHINGER ,  Gerald RESCHER ,  Francisco Javier SANTOS RODRIGUEZ ,  Carsten SCHAEFFER ,  Armin TILKE

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/16 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78

Abstract: A method for forming an interface layer on a silicon carbide body comprises removing an oxide layer from a surface of a silicon carbide body to obtain a silicon carbide surface. The silicon carbide body comprises a source region of a first conductivity type and a body region of a second conductivity type. The method further comprises after removing the oxide layer, depositing an interface layer directly on the silicon carbide surface. The interface layer has a thickness of less or equal to 15 nm. The method further comprises forming an electrical insulator over the interface layer, and forming a gate electrode over the electrical insulator.

公开(公告)号：US20240405092A1

公开(公告)日：2024-12-05

申请号：US18664904

申请日：2024-05-15

Applicant: Infineon Technologies AG

Inventor： Armin TILKE ,  Sandra KRAUSE ,  Thomas AICHINGER ,  Wolfgang LEHNERT ,  Francisco Javier SANTOS RODRIGUEZ

IPC: H01L29/51 ,  H01L29/16 ,  H01L29/423

Abstract: There is described a semiconductor device comprising an SiC body with a gate structure comprising a gate dielectric with a specific multilayer laminate structure including alternating layers of a first dielectric material and of a second dielectric material having a dielectric constant of 4 or higher. There is further described a method for manufacturing such a semiconductor device including an SiC body as mentioned before.

公开(公告)号：US20250089323A1

公开(公告)日：2025-03-13

申请号：US18827272

申请日：2024-09-06

Applicant: Infineon Technologies AG

Inventor： Thomas AICHINGER ,  Dethard PETERS ,  Michael HELL ,  Andreas HÜRNER

IPC: H01L29/16 ,  H01L29/43 ,  H01L29/51 ,  H01L29/78

Abstract: A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

公开(公告)号：US20250015148A1

公开(公告)日：2025-01-09

申请号：US18764822

申请日：2024-07-05

Applicant: Infineon Technologies AG

Inventor： Thomas AICHINGER ,  Wolfgang BERGNER ,  Hans WEBER ,  Michael HELL ,  Armin TILKE ,  Grazvydas ZIEMYS

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends at least as deep as the first trench into the semiconductor body.

公开(公告)号：US20210119006A1

公开(公告)日：2021-04-22

申请号：US17072602

申请日：2020-10-16

Applicant: Infineon Technologies AG

Inventor： Thomas AICHINGER ,  Wolfgang BERGNER ,  Ralf SIEMIENIEC ,  Frank WOLTER

IPC: H01L29/43 ,  H01L29/10 ,  H01L29/423 ,  H01L29/16

Abstract: In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.

公开(公告)号：US20170040425A1

公开(公告)日：2017-02-09

申请号：US15221122

申请日：2016-07-27

Applicant: Infineon Technologies AG

Inventor： Daniel KUECK ,  Thomas AICHINGER ,  Franz HIRLER ,  Anton MAUDER

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a source zone electrically connected to a first load terminal, a contiguous zone isolating the source zone from a drift zone, and a trench extending into a semiconductor body along a vertical direction and including a first electrode electrically connected to a control terminal and an insulator in contact with the contiguous zone and which isolates the first electrode from the semiconductor body. The insulator has, at a trench bottom region, a first thickness along the vertical direction, and, at a trench top region, a second thickness along a lateral direction, the first thickness being greater than the second thickness by a factor of at least 1.5. The contiguous zone is arranged in contact with the insulator and extends further along the vertical direction than the trench, and the trench bottom region and the contiguous zone overlap along the lateral direction.

Abstract translation: 半导体器件包括电连接到第一负载端子的源极区域，将源区域与漂移区隔离的连续区域以及沿着垂直方向延伸到半导体本体中的沟槽，并且包括电连接到控制端子的第一电极 以及与所述连续区域接触并将所述第一电极与所述半导体本体隔离的绝缘体。 绝缘体在沟槽底部区域沿着垂直方向具有第一厚度，并且在沟槽顶部区域处沿着横向方向具有第二厚度，第一厚度大于第二厚度至少为1.5倍 。 连续区域布置成与绝缘体接触并且沿着垂直方向进一步沿着沟槽延伸，并且沟槽底部区域和连续区域沿着横向方向重叠。