公开(公告)号：US11776996B2

公开(公告)日：2023-10-03

申请号：US17536253

申请日：2021-11-29

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Joost Adriaan Willemen

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/74 ,  H01L29/735 ,  H01L29/868

CPC classification number: H01L29/0649 ,  H01L29/0692 ,  H01L29/735 ,  H01L29/7436 ,  H01L29/868 ,  H01L29/8611

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, a plurality of n-type wells that each extend from the upper surface into the semiconductor body, first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body at least as deep as the p-type wells, and second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body at least as deep as the n-type wells, wherein the p-type wells and the n-type wells alternate with one another a first direction, and wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.

公开(公告)号：US20220094158A1

公开(公告)日：2022-03-24

申请号：US17027226

申请日：2020-09-21

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Joost Adriaan Willemen

IPC: H02H9/04 ,  H01L27/02

Abstract: An overvoltage protection device includes first and second semiconductor devices arranged in an anti-serial configuration with a conductive link connected between the first and second semiconductor devices at a central node of the overvoltage protection device, a first terminal connection to a terminal of the first semiconductor device that is opposite from the central node, a second terminal connection to a terminal of the second semiconductor device that is opposite from the central node. A total capacitance of elements in a first transmission path that is between the first terminal connection and the central node substantially matches a total capacitance of elements in a second transmission path that is between the second terminal connection and the central node. The total capacitance of elements in the second transmission path includes a self-capacitance of the conductive link.

公开(公告)号：US20240204516A1

公开(公告)日：2024-06-20

申请号：US18591681

申请日：2024-02-29

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Joost Adriaan Willemen

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0288

Abstract: An overvoltage protection device includes a semiconductor die, first and second semiconductor devices that are monolithically integrated in the semiconductor die and arranged in an anti-serial configuration with a conductive link connected between the first and second semiconductor devices at a central node of the overvoltage protection device, the first and second semiconductor devices each being two terminal semiconductor devices with one way conduction characteristics, a first conductive electrode connected to a terminal of the first semiconductor device that is opposite from the central node, a second conductive electrode connected to a terminal of the second semiconductor device that is opposite from the central node, a monolithically integrated feature of the semiconductor die that compensates for a parasitic capacitance of the overvoltage protection device such that the capacitances of the overvoltage protection device under operation are substantially symmetrical with respect to the central node.

公开(公告)号：US20230395656A1

公开(公告)日：2023-12-07

申请号：US18234992

申请日：2023-08-17

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Joost Adriaan Willemen

IPC: H01L29/06 ,  H01L29/735 ,  H01L29/74 ,  H01L29/861 ,  H01L29/868

CPC classification number: H01L29/0649 ,  H01L29/0692 ,  H01L29/868 ,  H01L29/7436 ,  H01L29/8611 ,  H01L29/735

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, and a plurality of n-type wells that each extend from the upper surface into the semiconductor body, wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.

公开(公告)号：US12255229B2

公开(公告)日：2025-03-18

申请号：US18234992

申请日：2023-08-17

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Joost Adriaan Willemen

IPC: H01L29/06 ,  H01L29/735 ,  H01L29/74 ,  H01L29/861 ,  H01L29/868

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, and a plurality of n-type wells that each extend from the upper surface into the semiconductor body, wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.

公开(公告)号：US20230307388A1

公开(公告)日：2023-09-28

申请号：US17702342

申请日：2022-03-23

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Isabella Goetz ,  Egle Tylaite

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L23/62 ,  H01L27/0248

Abstract: An overvoltage protection device includes a semiconductor body including a substrate region disposed beneath an upper surface of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a trenched connector formed in the semiconductor body, a vertical voltage blocking device formed in the semiconductor body, wherein the trenched connector includes a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, and a metal electrode disposed within the trench, wherein the metal electrode forms an electrically conductive connection between the first contact pad and the substrate region, and wherein the voltage blocking device is connected between the second contact pad and the substrate region.

公开(公告)号：US20230080466A1

公开(公告)日：2023-03-16

申请号：US17941684

申请日：2022-09-09

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Vadim Valentinovic Vendt ,  Joost Adriaan Willemen

IPC: H01L27/02 ,  H02H9/04

Abstract: A semiconductor device includes a semiconductor body, first and second contact pads disposed on an upper surface of the semiconductor body, a lateral ESD protection device formed in the semiconductor body, and a vertical ESD protection device formed in the semiconductor body, wherein the lateral ESD protection device and the vertical ESD protection device together form a unidirectional device between the first and second contact pads, and wherein the lateral ESD protection device is formed in a first portion of the semiconductor body that is laterally electrically isolated from a vertical current path of the vertical ESD protection device.

公开(公告)号：US12218084B2

公开(公告)日：2025-02-04

申请号：US17702342

申请日：2022-03-23

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Isabella Goetz ,  Egle Tylaite

IPC: H01L23/62 ,  H01L27/02

Abstract: An overvoltage protection device includes a semiconductor body including a substrate region disposed beneath an upper surface of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a trenched connector formed in the semiconductor body, a vertical voltage blocking device formed in the semiconductor body, wherein the trenched connector includes a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, and a metal electrode disposed within the trench, wherein the metal electrode forms an electrically conductive connection between the first contact pad and the substrate region, and wherein the voltage blocking device is connected between the second contact pad and the substrate region.

公开(公告)号：US11936178B2

公开(公告)日：2024-03-19

申请号：US17027226

申请日：2020-09-21

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Joost Adriaan Willemen

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0288

Abstract: An overvoltage protection device includes first and second semiconductor devices arranged in an anti-serial configuration with a conductive link connected between the first and second semiconductor devices at a central node of the overvoltage protection device, a first terminal connection to a terminal of the first semiconductor device that is opposite from the central node, a second terminal connection to a terminal of the second semiconductor device that is opposite from the central node. A total capacitance of elements in a first transmission path that is between the first terminal connection and the central node substantially matches a total capacitance of elements in a second transmission path that is between the second terminal connection and the central node. The total capacitance of elements in the second transmission path includes a self-capacitance of the conductive link.

公开(公告)号：US20230170385A1

公开(公告)日：2023-06-01

申请号：US17536253

申请日：2021-11-29

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Joost Adriaan Willemen

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/868 ,  H01L29/735 ,  H01L29/74

CPC classification number: H01L29/0649 ,  H01L29/8611 ,  H01L29/868 ,  H01L29/735 ,  H01L29/0692 ,  H01L29/7436

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, a plurality of n-type wells that each extend from the upper surface into the semiconductor body, first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body at least as deep as the p-type wells, and second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body at least as deep as the n-type wells, wherein the p-type wells and the n-type wells alternate with one another a first direction, and wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.