公开(公告)号：US20170076961A1

公开(公告)日：2017-03-16

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/56 ,  H01L27/02 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US09966277B2

公开(公告)日：2018-05-08

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L27/02 ,  H01L23/31 ,  H01L29/861

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

公开(公告)号：US20150221523A1

公开(公告)日：2015-08-06

申请号：US14598288

申请日：2015-01-16

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/3213 ,  H01L21/283 ,  H01L27/02 ,  H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L21/304

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US12218084B2

公开(公告)日：2025-02-04

申请号：US17702342

申请日：2022-03-23

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Isabella Goetz ,  Egle Tylaite

IPC: H01L23/62 ,  H01L27/02

Abstract: An overvoltage protection device includes a semiconductor body including a substrate region disposed beneath an upper surface of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a trenched connector formed in the semiconductor body, a vertical voltage blocking device formed in the semiconductor body, wherein the trenched connector includes a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, and a metal electrode disposed within the trench, wherein the metal electrode forms an electrically conductive connection between the first contact pad and the substrate region, and wherein the voltage blocking device is connected between the second contact pad and the substrate region.

公开(公告)号：US20230307388A1

公开(公告)日：2023-09-28

申请号：US17702342

申请日：2022-03-23

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Isabella Goetz ,  Egle Tylaite

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L23/62 ,  H01L27/0248

Abstract: An overvoltage protection device includes a semiconductor body including a substrate region disposed beneath an upper surface of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a trenched connector formed in the semiconductor body, a vertical voltage blocking device formed in the semiconductor body, wherein the trenched connector includes a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, and a metal electrode disposed within the trench, wherein the metal electrode forms an electrically conductive connection between the first contact pad and the substrate region, and wherein the voltage blocking device is connected between the second contact pad and the substrate region.

公开(公告)号：US09543208B2

公开(公告)日：2017-01-10

申请号：US14188355

申请日：2014-02-24

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Damian Sojka ,  Isabella Goetz

IPC: H01L21/762 ,  H01L21/82 ,  H01L21/765 ,  H01L29/06 ,  H01L21/301

CPC classification number: H01L21/82 ,  H01L21/76224 ,  H01L21/765 ,  H01L21/78 ,  H01L29/0649

Abstract: In accordance with an embodiment of the present invention, a method for forming a semiconductor device includes forming a device region in a substrate. The device region extends continuously from one sidewall of the substrate to an opposite sidewall of the substrate. The method further includes forming trenches in the substrate. The trenches divide the device region into active regions. The method also includes singulating the substrate by separating the substrate along the trenches.

Abstract translation: 根据本发明的实施例，一种用于形成半导体器件的方法包括在衬底中形成器件区域。 器件区域从衬底的一个侧壁连续延伸到衬底的相对侧壁。 该方法还包括在衬底中形成沟槽。 沟槽将设备区域划分为活动区域。 该方法还包括通过沿着沟槽分离衬底来分离衬底。

公开(公告)号：US20150243561A1

公开(公告)日：2015-08-27

申请号：US14188355

申请日：2014-02-24

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Damian Sojka ,  Isabella Goetz

IPC: H01L21/82 ,  H01L29/06 ,  H01L21/765

CPC classification number: H01L21/82 ,  H01L21/76224 ,  H01L21/765 ,  H01L21/78 ,  H01L29/0649

Abstract: In accordance with an embodiment of the present invention, a method for forming a semiconductor device includes forming a device region in a substrate. The device region extends continuously from one sidewall of the substrate to an opposite sidewall of the substrate. The method further includes forming trenches in the substrate. The trenches divide the device region into active regions. The method also includes singulating the substrate by separating the substrate along the trenches.

Abstract translation: 根据本发明的实施例，一种用于形成半导体器件的方法包括在衬底中形成器件区域。 器件区域从衬底的一个侧壁连续延伸到衬底的相对侧壁。 该方法还包括在衬底中形成沟槽。 沟槽将设备区域划分为活动区域。 该方法还包括通过沿着沟槽分离衬底来分离衬底。