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公开(公告)号：US12248088B2
公开(公告)日：2025-03-11
申请号：US17541687
申请日：2021-12-03
Applicant: Infineon Technologies AG
Inventor： Rainer Findenig , Bernhard Greslehner-Nimmervoll , Grigory Itkin , Markus Josef Lang , Ulrich Moeller , Martin Wiessflecker
Abstract: A radar semiconductor chip includes a radar circuit component configured to generate at least part of a frequency-modulated ramp signal or process at least part of a reflected frequency-modulated ramp signal according to a control parameter; a memory configured to store a sequencing program associated with regulating the control parameter, wherein the sequencing program specifies a first data source, external to the sequencing program, that is configured to provide a first data value corresponding to the control parameter; and a decoder configured to read the sequencing program, access the first data value from the first data source specified by the sequencing program, derive a first control value for the control parameter from the first data value, and provide the first control value to the radar circuit component. The radar circuit component regulates a controlled circuit function in accordance with the control parameter based on the first control value.
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公开(公告)号：US11668792B2
公开(公告)日：2023-06-06
申请号：US16946978
申请日：2020-07-14
Applicant: Infineon Technologies AG
Inventor： Grigory Itkin
CPC classification number: G01S7/40 , G01S7/4021 , H03H7/38
Abstract: A device may include a receive antenna input to couple a receive chain of the device to a receive antenna. The device may include a test signal generator. The device may include a switchable impedance matching circuit coupled to the test signal generator and to the receive chain to cause an impedance matching between the test signal generator and at least one component of the receive chain to depend on an impedance of the receive antenna in an antenna monitoring phase. The antenna monitoring phase may be associated with determining an impedance mismatching of the receive antenna. The device may include a control circuit to determine the impedance mismatching of the receive antenna in the antenna monitoring phase.
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公开(公告)号：US11567170B2
公开(公告)日：2023-01-31
申请号：US16850605
申请日：2020-04-16
Applicant: Infineon Technologies AG
Inventor： Grigory Itkin , Michael Jung
Abstract: A method for calibrating a radar system includes generating an RF oscillator signal and distributing the RF oscillator signal to a plurality of phase shifters each providing a respective phase-shifted RF oscillator signal; receiving the phase-shifted RF oscillator signals by corresponding radar chips and radiating the phase-shifted RF oscillator signal via a first RF output channel of a first one of the radar chips; receiving a back-scattered signal by at least one RF input channel of each radar chip and generating a plurality of base-band signals by down-converting the received signals into a base band using the phase-shifted RF oscillator signals received by the corresponding radar chips; determining a phase for each base-band signal; and adjusting the phase shifts caused by the phase shifters such that the phases of the base-band signals match a predefined phase-over-antenna-position characteristic.
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公开(公告)号：US11221398B2
公开(公告)日：2022-01-11
申请号：US16545879
申请日：2019-08-20
Applicant: Infineon Technologies AG
Inventor： Grigory Itkin
Abstract: A device may include a test signal generator and a receive antenna input. The device may include a switchable impedance matching circuit, coupled to the test signal generator and to a receive chain, to cause an impedance matching between the test signal generator and a component of the receive chain to be increased during a monitoring phase. The impedance matching during the monitoring phase enables one or more measurements based on a test signal generated by the test signal generator. The switchable impedance matching circuit may cause a partial impedance mismatching between the test signal generator and the component of the receive chain during a verification phase associated with verifying a return of the switchable impedance matching circuit to an impedance matching caused during the operational phase. The device may include a control circuit to verify operation of the returning of the switchable impedance matching circuit in the verification phase.
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公开(公告)号：US11815624B2
公开(公告)日：2023-11-14
申请号：US17571767
申请日：2022-01-10
Applicant: Infineon Technologies AG
Inventor： Grigory Itkin
CPC classification number: G01S7/4021 , G01S7/40 , H01Q23/00 , H03H11/28
Abstract: A device may include a test signal generator and a receive antenna input. The device may include a switchable impedance matching circuit, coupled to the test signal generator and to a receive chain, to cause an impedance matching between the test signal generator and a component of the receive chain to be increased during a monitoring phase. The impedance matching during the monitoring phase enables one or more measurements based on a test signal generated by the test signal generator. The switchable impedance matching circuit may cause a partial impedance mismatching between the test signal generator and the component of the receive chain during a verification phase associated with verifying a return of the switchable impedance matching circuit to an impedance matching caused during the operational phase. The device may include a control circuit to verify operation of the returning of the switchable impedance matching circuit in the verification phase.
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Patent Agency Ranking
公开(公告)号：US11353547B2
公开(公告)日：2022-06-07
申请号：US16863326
申请日：2020-04-30
Applicant: Infineon Technologies AG
Inventor： Grigory Itkin
IPC: G01S7/292
Abstract: A radar system is provided. The radar system includes a first radar chip, a second radar chip and a third radar chip. Further, the second radar chip includes a first coupling circuit. Additionally, the third radar chip includes a second coupling circuit. A control circuit is configured to control the first coupling circuit and the second coupling circuit. The first radar chip includes an analysis circuit configured to determine information indicating a reflected wave component. The analysis circuit is further configured to determine, based on the determined information, whether distributions of the oscillation signal to the first and second input nodes via the first and second signal lines are equal.
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公开(公告)号：US11251785B1
公开(公告)日：2022-02-15
申请号：US17215880
申请日：2021-03-29
Applicant: Infineon Technologies AG
Inventor： Grigory Itkin
IPC: G05F1/10 , G05F3/02 , H03K5/1252 , H02M3/155 , H03K5/00
Abstract: An integrated circuit includes a first input port configured to receive a supply voltage from a switched-mode power supply (SMPS), where frequency components of the supply voltage include harmonics of a reference frequency, where the reference frequency is equal to a first frequency divided by a factor; and a spurious components cancellation circuit coupled to the first input port, where the spurious components cancellation circuit is configured to: generate a first clock signal having the reference frequency; adjust an amplitude and a phase of the first clock signal to form a compensation signal; and add the compensation signal to the supply voltage to produce a modified supply voltage with reduced frequency components at one or more harmonic frequencies of the reference frequency.
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公开(公告)号：US20200150258A1
公开(公告)日：2020-05-14
申请号：US16184699
申请日：2018-11-08
Applicant: Infineon Technologies AG
Inventor： Grigory Itkin
Abstract: A phase-locked loop (PLL) for a radar system includes an oscillator configured to have an output frequency and a multi-modulus divider (MMD) configured to implement successive frequency modulation ramps of the oscillator output frequency, each frequency modulation ramp beginning at a first frequency and ending at a second frequency. The PLL is operated by downmixing an output of the MMD to a frequency above zero Hertz, measuring the downmixed output of the MMD to generate a plurality of MMD output measurements for each frequency modulation ramp, and calculating the frequency of the MMD based on the plurality of MMD output measurements for each frequency modulation ramp.
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公开(公告)号：US11977180B2
公开(公告)日：2024-05-07
申请号：US17360082
申请日：2021-06-28
Applicant: Infineon Technologies AG
Inventor： Grigory Itkin , Stefan Herzinger
IPC: G01S7/40
CPC classification number: G01S7/40 , G01S7/4021
Abstract: A radar system includes a signal generator configured to generate an RF signal; a modulator configured to generate an RF test signal by modulating the RF signal with a test signal; a transmitting channel configured to generate an RF output signal based on the RF signal; and a receiving channel configured to receive an antenna signal and the RF test signal and down-convert a superposition of the two signals to baseband by means of a mixer in order to obtain a baseband signal. The radar system further includes an analog-to-digital converter configured to generate a digital radar signal based on the baseband signal, and a computing unit configured to filter the digital radar signal by means of a digital filter, wherein the filter characteristic of the digital filter has a pass band, a transition band, and a stop band. The test signal has a frequency in the transition band.
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10.发明授权公开(公告)号：US11223364B2
公开(公告)日：2022-01-11
申请号：US16676869
申请日：2019-11-07
Applicant: Infineon Technologies AG
Inventor： Grigory Itkin
Abstract: A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.
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