公开(公告)号：US20250130270A1

公开(公告)日：2025-04-24

申请号：US18908105

申请日：2024-10-07

Applicant: Infineon Technologies AG

Inventor： Guang Zeng ,  Dethard Peters

IPC: G01R31/26

Abstract: A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device each including a load path and a control node, and each at least partially integrated in a semiconductor body. The load paths of the first and second transistor devices are connected in parallel. The transistor arrangement further includes a first control pad connected to the control node of the first transistor device through a first resistor, and a second control pad connected to the control node of the second transistor device and connected to the first control pad through a second resistor.

公开(公告)号：US12278231B2

公开(公告)日：2025-04-15

申请号：US17692509

申请日：2022-03-11

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Guang Zeng

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/16

Abstract: An apparatus includes a junction termination edge, a unipolar power transistor, and an RC snubber. The RC snubber has a capacitor between a poly silicon structure and a semiconductor substrate, and part of the junction termination edge. The capacitor has a p-n junction. The RC snubber has a poly silicon resistor between a source of the unipolar power transistor and a first layer forming the capacitor. The unipolar transistor and the RC snubber are coupled in parallel. The RC snubber and the unipolar power transistor are formed monolithically on the semiconductor substrate.

公开(公告)号：US11876509B1

公开(公告)日：2024-01-16

申请号：US17875876

申请日：2022-07-28

Applicant: Infineon Technologies AG

Inventor： Guang Zeng ,  Franz-Josef Niedernostheide ,  Mark-Matthias Bakran ,  Zheming Li

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687

CPC classification number: H03K17/166 ,  H03K17/168 ,  H03K17/687 ,  H03K2217/0027

Abstract: A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

公开(公告)号：US20220406928A1

公开(公告)日：2022-12-22

申请号：US17838490

申请日：2022-06-13

Applicant: Infineon Technologies AG

Inventor： Joachim Weyers ,  Anton Mauder ,  Ralf Siemieniec ,  Guang Zeng

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06

Abstract: A semiconductor device includes a transistor cell with a source region of a first conductivity type and a gate electrode. The source region is formed in a wide bandgap semiconductor portion. A diode chain includes a plurality of diode structures. The diode structures are formed in the wide bandgap semiconductor portion and electrically connected in series. Each diode structure includes a cathode region of the first conductivity type and an anode region of a complementary second conductivity type. A gate metallization is electrically connected with the gate electrode and with a first one of the anode regions in the diode chain. A source electrode structure is electrically connected with the source region and with a last one of the cathode regions in the diode chain.

公开(公告)号：US20240290878A1

公开(公告)日：2024-08-29

申请号：US18585167

申请日：2024-02-23

Applicant: Infineon Technologies AG

Inventor： Guang Zeng ,  Dethard Peters

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L29/66734

Abstract: A vertical power semiconductor device includes a semiconductor body having first and second opposite surfaces. A subdivision of an area of the semiconductor body at the first surface includes: a transistor cell area having transistor cells in the semiconductor body; an edge termination area surrounding the transistor cell area, the semiconductor body including a termination structure in the edge termination area; a gate line area between the transistor cell area and the edge termination area, the gate line area including a gate line over the semiconductor body; and a source or emitter line area between the gate line area and the edge termination area. The source or emitter line area includes transistor cells in the semiconductor body, and a source or emitter line over the semiconductor body.