公开(公告)号：US09722659B2

公开(公告)日：2017-08-01

申请号：US15069098

申请日：2016-03-14

Applicant: Infineon Technologies AG

Inventor： Christian Unhold

IPC: H04L7/00 ,  H04L7/04 ,  H03D3/24 ,  H04B1/69 ,  H03L7/00

CPC classification number: H04B1/69 ,  H03L7/00 ,  H03L7/1976 ,  H04B2001/6912

Abstract: A method for generating a digital frequency ramp signal including a sequence of frequency ramps is disclosed herein. In accordance with one embodiment of the present invention the method comprises loading a first data word of a data record from a memory. The data record includes information associated with a first frequency ramp, wherein the first data word of the data record includes a header. The method further includes the evaluation of the header to determine whether, or not, the data record includes one or more additional data words and to determine, which information is included in the additional data word(s). Dependent on the evaluation of the header, the additional data word(s) of the data record are loaded from the memory. In accordance with the information stored in the first data word and, if loaded, the additional data word(s) ramp parameters and/or configuration parameters are updated. The method includes, moreover, generating digital ramp signal values in accordance with the updated ramp parameters and synchronous to a clock signal.

公开(公告)号：US08908748B2

公开(公告)日：2014-12-09

申请号：US13651559

申请日：2012-10-15

Applicant: Infineon Technologies AG

Inventor： Klaus Buchner ,  Klemens Kordik ,  Christian Unhold

IPC: H04B1/38 ,  G06F13/40 ,  H04L29/10 ,  G11C16/10 ,  G06F13/42

CPC classification number: H04L29/10 ,  G06F13/4072 ,  G06F13/4291 ,  G11C16/10

Abstract: An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition.

Abstract translation: 接口电路包括接口端子，电压检测装置，输出驱动器和使能逻辑。 接口终端配置为连接到接口线。 电压检测装置被配置为检测存在于接口端子处的电压。 输出驱动器被配置为向接口终端施加输出信号。 使能逻辑被配置为基于由电压检测装置输出的评估信号来产生用于输出驱动器的使能信号，其中如果评估信号示出存在于接口端子处的电压，则使能信号影响输出驱动器的使能 满足一定条件。

公开(公告)号：US20130094559A1

公开(公告)日：2013-04-18

申请号：US13651559

申请日：2012-10-15

Applicant: infineon Technologies AG

Inventor： Klaus Buchner ,  Klemens Kordik ,  Christian Unhold

IPC: H04B3/46 ,  H04B3/00

CPC classification number: H04L29/10 ,  G06F13/4072 ,  G06F13/4291 ,  G11C16/10

Abstract: An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition.

Abstract translation: 接口电路包括接口端子，电压检测装置，输出驱动器和使能逻辑。 接口终端配置为连接到接口线。 电压检测装置被配置为检测存在于接口端子处的电压。 输出驱动器被配置为向接口终端施加输出信号。 使能逻辑被配置为基于由电压检测装置输出的评估信号来产生用于输出驱动器的使能信号，其中如果评估信号示出存在于接口端子处的电压，则使能信号影响输出驱动器的使能 满足一定条件。