公开(公告)号：US20240243042A1

公开(公告)日：2024-07-18

申请号：US18097358

申请日：2023-01-16

Applicant: Infineon Technologies AG

Inventor： Tillmann Walther ,  Markus Neubert ,  Andrey Kravchenko ,  Christian Schweikert

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49568 ,  H01L23/49558 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48091

Abstract: A power semiconductor module includes: an electrically insulative frame; a plurality of power semiconductor dies housed within the electrically insulative frame and electrically interconnected to form a power electronics circuit; an active temperature sensor die housed within the electrically insulative frame and including an integrated current source; a first temperature sense terminal electrically connected to a first contact pad of the active temperature sensor die; and a second temperature sense terminal electrically connected to a second contact pad of the active temperature sensor die. A discrete power semiconductor device and methods of producing the module and discrete device are also described.

公开(公告)号：US20240079297A1

公开(公告)日：2024-03-07

申请号：US17903512

申请日：2022-09-06

Applicant: Infineon Technologies AG

Inventor： Peter Luniewski ,  Markus Neubert ,  Michael Fuegl ,  Waldemar Jakobi ,  Michael Leipenat ,  Egbert Lamminger

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49562 ,  H01L24/48 ,  H01L2224/48245

Abstract: A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.