公开(公告)号：US20180115321A1

公开(公告)日：2018-04-26

申请号：US15716252

申请日：2017-09-26

Applicant: Infineon Technologies AG

Inventor： Michael Kropfitsch ,  Massimo Rigo

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/43 ,  H03M3/456 ,  H03M3/464

Abstract: A sigma delta analog to digital converter for converting an analog input into a digital output comprises a reference path for receiving a reference voltage. The reference path comprises a digital to analog converter. The digital to analog converter comprises a reference voltage input for receiving the reference voltage, wherein the reference voltage input comprises two contacts and wherein each contact is a beginning of a voltage line of two voltage lines. The digital to analog converter comprises a plurality of switches and a plurality of capacitors. The switches of the plurality of switches are configured to connect the digital to analog converter in a sampling phase with the reference voltage and to disconnect the digital to analog converter in an integrating phase from the reference voltage.

公开(公告)号：US10601439B2

公开(公告)日：2020-03-24

申请号：US16287558

申请日：2019-02-27

Applicant: Infineon Technologies AG

Inventor： Martin Pernull ,  Massimo Rigo ,  Herwig Wappis

IPC: H03M3/00 ,  H03M1/38 ,  H03M1/12

Abstract: Sigma-delta converters having a sampling circuit are provided. The sampling circuit is actuated such that sampling times are at least partially random.

公开(公告)号：US20190268014A1

公开(公告)日：2019-08-29

申请号：US16287558

申请日：2019-02-27

Applicant: Infineon Technologies AG

Inventor： Martin Pernull ,  Massimo Rigo ,  Herwig Wappis

IPC: H03M3/00 ,  H03M1/12 ,  H03M1/38

Abstract: Sigma-delta converters having a sampling circuit are provided. The sampling circuit is actuated such that sampling times are at least partially random.

公开(公告)号：US10044368B2

公开(公告)日：2018-08-07

申请号：US15716252

申请日：2017-09-26

Applicant: Infineon Technologies AG

Inventor： Michael Kropfitsch ,  Massimo Rigo

IPC: H03M3/00

Abstract: A sigma delta analog to digital converter for converting an analog input into a digital output comprises a reference path for receiving a reference voltage. The reference path comprises a digital to analog converter. The digital to analog converter comprises a reference voltage input for receiving the reference voltage, wherein the reference voltage input comprises two contacts and wherein each contact is a beginning of a voltage line of two voltage lines. The digital to analog converter comprises a plurality of switches and a plurality of capacitors. The switches of the plurality of switches are configured to connect the digital to analog converter in a sampling phase with the reference voltage and to disconnect the digital to analog converter in an integrating phase from the reference voltage.