公开(公告)号：US20180122720A1

公开(公告)日：2018-05-03

申请号：US15796771

申请日：2017-10-28

Applicant: Infineon Technologies AG

Inventor： Wolfram HABLE ,  Andreas GRASSMANN ,  Juergen HOEGERL ,  Eduard KNAUER ,  Michael LEDUTKE

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3675 ,  B60L11/18 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/48 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/33181 ,  H01L2224/48229 ,  H01L2224/4823 ,  H01L2224/48237 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/14252 ,  H01L2924/30107 ,  H02M7/003

Abstract: A package comprising at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, a first electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one first terminal of at least one of the at least one electronic chip, and a second electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one second terminal of at least one of the at least one electronic chip, wherein at least a portion of the first electrically conductive contact structure and at least a portion of the second electrically conductive contact structure within the encapsulant are spaced in a direction between two opposing main surfaces of the package.

公开(公告)号：US20220415745A1

公开(公告)日：2022-12-29

申请号：US17361823

申请日：2021-06-29

Applicant: Infineon Technologies AG

Inventor： Adrian LIS ,  Michael LEDUTKE

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L21/48

Abstract: One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.

公开(公告)号：US20190074198A1

公开(公告)日：2019-03-07

申请号：US16118651

申请日：2018-08-31

Applicant: Infineon Technologies AG

Inventor： Kristina MAYER ,  Michael LEDUTKE ,  Johannes LODERMEYER

IPC: H01L21/56 ,  H01L23/00

Abstract: A method comprises: arranging a plurality of semiconductor chips above a carrier, wherein active main surfaces of the semiconductor chips face the carrier; filling a cavity with a molding material; pressing the semiconductor chips arranged on the carrier into the molding material; and separating the molding material with the semiconductor chips embedded therein from the carrier, wherein main surfaces of the semiconductor chips that are situated opposite the active main surfaces are covered by the molding material.