公开(公告)号：US20150089333A1

公开(公告)日：2015-03-26

申请号：US14492204

申请日：2014-09-22

Applicant: Infineon Technologies AG

Inventor： Sven Hosp ,  Michael Goessel ,  Klaus Oberlaender

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  H03M13/19 ,  H03M13/6502

Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.

Abstract translation: 一种用于确定m个校验位c1，...的电路装置。 。 。 ，k表示k个数据位u1，。 。 。 提供uk，其中电路装置包括第一分支电路和第二分支电路。 第一个子电路具有用于输入k个数据位u = u1的k个二进制输入。 。 。 ，uk和M二进制输出，用于输出M个二进制中间值z1，。 。 。 ，zM从数据位确定。 第二分支电路被配置成转换中间值z1，。 。 。 ，zM进入校验位c1，。 。 。 ， 厘米。

公开(公告)号：US09646716B2

公开(公告)日：2017-05-09

申请号：US14447806

申请日：2014-07-31

Applicant: Infineon Technologies AG

Inventor： Michael Goessel ,  Sven Hosp ,  Guenther Niess ,  Klaus Oberlaender

IPC: H03M13/11 ,  G11C29/10 ,  G06F11/263 ,  G11C29/42 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/10 ,  G06F11/1048 ,  G06F11/263 ,  G11C29/42 ,  G11C2029/0411

Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C). Furthermore, the error detection circuit (12) is designed, for the case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset (M) of bits was written to the memory location, to determine on the basis of the data word read out from the memory (11) whether a memory error is present if the code word that is inverted in the subset (M) of bits is not a code word of the error detection code (C).

公开(公告)号：US09645883B2

公开(公告)日：2017-05-09

申请号：US14492204

申请日：2014-09-22

Applicant: Infineon Technologies AG

Inventor： Sven Hosp ,  Michael Goessel ,  Klaus Oberlaender

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/19

CPC classification number: G06F11/1004 ,  H03M13/19 ,  H03M13/6502

Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.

公开(公告)号：US20150039952A1

公开(公告)日：2015-02-05

申请号：US14447806

申请日：2014-07-31

Applicant: Infineon Technologies AG

Inventor： Michael Goessel ,  Sven Hosp ,  Guenther Niess ,  Klaus Oberlaender

IPC: G11C29/10 ,  G06F11/263

CPC classification number: G11C29/10 ,  G06F11/1048 ,  G06F11/263 ,  G11C29/42 ,  G11C2029/0411

Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C). Furthermore, the error detection circuit (12) is designed, for the case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset (M) of bits was written to the memory location, to determine on the basis of the data word read out from the memory (11) whether a memory error is present if the code word that is inverted in the subset (M) of bits is not a code word of the error detection code (C).

Abstract translation: 提供了一种用于检测存储器错误的电路装置。 电路装置包括存储器（11）和错误检测电路（12）。 电路装置被设计成存储错误检测码（C）的代码字或在存储器（11）中在存储器（11）的位的子集（M））中反转的代码字，并读出数据字 从存储器（11）从存储器位置。 如果数据字不是错误检测码（C）的代码字，则对于存在的控制信号呈现第一值的情况，错误检测电路（12）被设计为指示存储器错误。 此外，对于存在的控制信号呈现与第一值不同的第二值，并且在位的子集（M）中被反转的代码字被写入的情况下，设计错误检测电路（12） 到存储器位置，基于从存储器（11）读出的数据字来确定是否存在存储器错误，如果在位的子集（M）中被反转的代码字不是存储器的代码字 错误检测码（C）。