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    METHOD FOR TESTING A MEMORY AND MEMORY SYSTEM
    1.
    发明申请
    METHOD FOR TESTING A MEMORY AND MEMORY SYSTEM 有权
    测试存储器和存储器系统的方法

    公开(公告)号：US20140372814A1

    公开(公告)日：2014-12-18

    申请号：US14301538

    申请日：2014-06-11

    Applicant: Infineon Technologies AG

    Inventor： Klaus Oberlaender

    IPC: G11C29/12

    CPC classification number: G11C29/12 ,  G06F11/1048 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

    Abstract: A method for testing a memory includes performing an error correction code check (ECC check) on user data stored in the memory, inverting the user data stored in the memory, performing a further ECC check on the inverted user data stored in the memory, and inverting the inverted user data stored in the memory for restoring the user data in the memory.

    Abstract translation: 用于测试存储器的方法包括对存储在存储器中的用户数据执行纠错码校验（ECC校验），反转存储在存储器中的用户数据，对存储在存储器中的反相用户数据执行另外的ECC校验，以及 反转存储在存储器中的反向用户数据，用于恢复存储器中的用户数据。

    Processing of data
    3.
    发明授权
    Processing of data 有权

    公开(公告)号：US11556412B2

    公开(公告)日：2023-01-17

    申请号：US16663839

    申请日：2019-10-25

    Applicant: Infineon Technologies AG

    Inventor： Christian Badack ,  Jessica Trebst ,  Michael Goessel ,  Klaus Oberlaender

    IPC: G06F11/10 ,  G06F9/38 ,  H03M13/00 ,  H03M13/15 ,  H03M13/13

    Abstract: A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

    CIRCUIT ARRANGEMENT AND METHOD FOR REALIZING CHECK BIT COMPACTING FOR CROSS PARITY CODES
    4.
    发明申请
    CIRCUIT ARRANGEMENT AND METHOD FOR REALIZING CHECK BIT COMPACTING FOR CROSS PARITY CODES 有权
    电路布置和实现针对交叉奇偶校验码检查位的方法

    公开(公告)号：US20150089333A1

    公开(公告)日：2015-03-26

    申请号：US14492204

    申请日：2014-09-22

    Applicant: Infineon Technologies AG

    Inventor： Sven Hosp ,  Michael Goessel ,  Klaus Oberlaender

    IPC: G06F11/10

    CPC classification number: G06F11/1004 ,  H03M13/19 ,  H03M13/6502

    Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.

    Abstract translation: 一种用于确定m个校验位c1，...的电路装置。 。 。 ，k表示k个数据位u1，。 。 。 提供uk，其中电路装置包括第一分支电路和第二分支电路。 第一个子电路具有用于输入k个数据位u = u1的k个二进制输入。 。 。 ，uk和M二进制输出，用于输出M个二进制中间值z1，。 。 。 ，zM从数据位确定。 第二分支电路被配置成转换中间值z1，。 。 。 ，zM进入校验位c1，。 。 。 ， 厘米。

    Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories
    6.
    发明授权
    Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories 有权

    公开(公告)号：US09646716B2

    公开(公告)日：2017-05-09

    申请号：US14447806

    申请日：2014-07-31

    Applicant: Infineon Technologies AG

    Inventor： Michael Goessel ,  Sven Hosp ,  Guenther Niess ,  Klaus Oberlaender

    IPC: H03M13/11 ,  G11C29/10 ,  G06F11/263 ,  G11C29/42 ,  G06F11/10 ,  G11C29/04

    CPC classification number: G11C29/10 ,  G06F11/1048 ,  G06F11/263 ,  G11C29/42 ,  G11C2029/0411

    Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C). Furthermore, the error detection circuit (12) is designed, for the case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset (M) of bits was written to the memory location, to determine on the basis of the data word read out from the memory (11) whether a memory error is present if the code word that is inverted in the subset (M) of bits is not a code word of the error detection code (C).

    Continuous error coding
    8.
    发明授权
    Continuous error coding 有权

    公开(公告)号：US11182246B1

    公开(公告)日：2021-11-23

    申请号：US16940751

    申请日：2020-07-28

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Christian Badack ,  Michael Goessel ,  Klaus Oberlaender

    IPC: G06F11/10 ,  G06F11/30 ,  G06F11/07

    Abstract: Systems, methods, and circuitries are disclosed for protecting data throughout read and write operations. In one example a method includes receiving a plurality of data bits; dividing the plurality of data bits into at least two data blocks; generating respective sets of block check bits for each respective data block using a respective first error code; combining the sets of block check bits to generate a set of signature bits for the plurality of data bits; generating a set of cumulative check bits for the plurality of data bits and the set of signature bits using a second error code; and storing, in a memory location, the plurality of data bits, the set of signature bits, and the set of cumulative check bits.

    DETECTING ADDRESS ERRORS
    9.
    发明申请
    DETECTING ADDRESS ERRORS 审中-公开

    公开(公告)号：US20200371864A1

    公开(公告)日：2020-11-26

    申请号：US16881473

    申请日：2020-05-22

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Klaus Oberlaender ,  Christian Badack ,  Michael Goessel

    IPC: G06F11/10 ,  G06F11/30 ,  G06F11/34 ,  H03M13/11

    Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.

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