公开(公告)号：US20150069424A1

公开(公告)日：2015-03-12

申请号：US14020391

申请日：2013-09-06

申请人： Infineon Technologies AG

发明人： Joost Willemen ,  Michael Mayerhofer ,  Ulrich Glaser ,  Yiqun Cao ,  Andreas Meiser ,  Magnus-Maria Hell ,  Matthias Stecher ,  Julien Lebon

IPC分类号： H01L31/173 ,  H01L27/02

CPC分类号： H01L31/173 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/15 ,  H01L29/808 ,  H02H3/20

摘要： A semiconductor component includes an auxiliary semiconductor device configured to emit radiation. The semiconductor component further includes a semiconductor device. An electrical coupling and an optical coupling between the auxiliary semiconductor device and the semiconductor device are configured to trigger emission of radiation by the auxiliary semiconductor device and to trigger avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device. The semiconductor device includes a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer.

摘要翻译： 半导体部件包括被配置为发射辐射的辅助半导体器件。 半导体部件还包括半导体器件。 辅助半导体器件和半导体器件之间的电耦合和光耦合被配置为触发辅助半导体器件的辐射发射，并通过吸收半导体器件中的辐射来触发半导体器件中的雪崩击穿。 半导体器件包括埋在半导体主体的表面下方的第一导电类型的第一层和布置在表面和第一层之间的第二导电类型的掺杂半导体区域之间的pn结。

公开(公告)号：US09953968B2

公开(公告)日：2018-04-24

申请号：US14628823

申请日：2015-02-23

申请人： Infineon Technologies AG

发明人： Yiqun Cao ,  Ulrich Glaser ,  Magnus-Maria Hell ,  Julien Lebon ,  Michael Mayerhofer ,  Andreas Meiser ,  Matthias Stecher ,  Joost Willemen

IPC分类号： H02H9/04 ,  H01L27/02

CPC分类号： H01L27/0255 ,  H01L27/0292 ,  H02H9/046

摘要： An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than −10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than −10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.

公开(公告)号：US09263619B2

公开(公告)日：2016-02-16

申请号：US14020391

申请日：2013-09-06

申请人： Infineon Technologies AG

发明人： Joost Willemen ,  Michael Mayerhofer ,  Ulrich Glaser ,  Yiqun Cao ,  Andreas Meiser ,  Magnus-Maria Hell ,  Matthias Stecher ,  Julien Lebon

IPC分类号： H01L27/15 ,  H01L31/173 ,  H01L27/02

CPC分类号： H01L31/173 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/15 ,  H01L29/808 ,  H02H3/20

摘要： A semiconductor component includes an auxiliary semiconductor device configured to emit radiation. The semiconductor component further includes a semiconductor device. An electrical coupling and an optical coupling between the auxiliary semiconductor device and the semiconductor device are configured to trigger emission of radiation by the auxiliary semiconductor device and to trigger avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device. The semiconductor device includes a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer.

摘要翻译： 半导体部件包括被配置为发射辐射的辅助半导体器件。 半导体部件还包括半导体器件。 辅助半导体器件和半导体器件之间的电耦合和光耦合被配置为触发辅助半导体器件的辐射发射，并通过吸收半导体器件中的辐射来触发半导体器件中的雪崩击穿。 半导体器件包括埋在半导体主体的表面下方的第一导电类型的第一层和布置在表面和第一层之间的第二导电类型的掺杂半导体区域之间的pn结。

公开(公告)号：US10263419B2

公开(公告)日：2019-04-16

申请号：US15183049

申请日：2016-06-15

申请人： Infineon Technologies AG

发明人： Yiqun Cao

IPC分类号： H02H9/04 ,  H01L25/16 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/866 ,  H01L29/78

摘要： A transient voltage protection circuit includes a first input/output pad, a second input/output pad, and a trigger circuit coupled between the first input/output pad and the second input/output pad. The trigger circuit includes a first trigger element which includes a first input/output node, a second input/output node, a third input/output node, and a first substrate diode coupled to the third input/output node of the first trigger element. The trigger circuit further includes a first resistor coupled between the first input/output node of the first trigger element and the second input/output node of the first trigger element. The trigger circuit further includes a second trigger element which includes a first input/output node, a second input/output node, a third input/output node, wherein the second input/output node of the first trigger element is coupled to the first input/output node of the second trigger element, and a second substrate diode coupled to the third input/output node of the second trigger element. The trigger circuit further includes a second resistor coupled between the first input/output node of the second trigger element and the second input/output node of the second trigger element.

公开(公告)号：US20150249078A1

公开(公告)日：2015-09-03

申请号：US14628823

申请日：2015-02-23

申请人： Infineon Technologies AG

发明人： Yiqun Cao ,  Ulrich Glaser ,  Magnus-Maria Hell ,  Julien Lebon ,  Michael Mayerhofer ,  Andreas Meiser ,  Matthias Stecher ,  Joost Willemen

IPC分类号： H01L27/02

CPC分类号： H01L27/0255 ,  H01L27/0292 ,  H02H9/046

摘要： An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than −10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than −10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.

摘要翻译： 描述具有ESD保护结构的集成电路。 一个实施例包括与第一端子和第二端子互连的电路部分，并且可在第一端子和第二端子之间的电压差大于+ 10V且小于-10V的情况下工作。集成电路还包括ESD保护 结构可操作以保护电路部分免受第一端子和第二端子之间的静电放电。 ESD保护结构可以在第一和第二端子之间的电压差大于+10V且小于-10V而不触发。 ESD保护结构电光学耦合到光子源，使得在ESD脉冲负载时由光子源发射的光子在ESD保护结构中是可吸收的，并且雪崩击穿可由吸收的光子产生的电子 - 空穴对引发。

公开(公告)号：US09891268B2

公开(公告)日：2018-02-13

申请号：US14800535

申请日：2015-07-15

申请人： Infineon Technologies AG

发明人： Julien Lebon ,  Yiqun Cao ,  Ulrich Glaser

IPC分类号： G01R31/00 ,  G01R31/28

CPC分类号： G01R31/2841 ,  G01R31/002

摘要： An apparatus and a method for generating signals for ESD stress testing an electronic device are disclosed. In an embodiment the apparatus is configured to receive a source signal including a source pulse, delay the source pulse to generate a test signal including a test pulse with a pulse width in an ESD time range and generate an auxiliary signal including an auxiliary pulse with a pulse width in the ESD time range.

公开(公告)号：US20170016945A1

公开(公告)日：2017-01-19

申请号：US14800535

申请日：2015-07-15

申请人： Infineon Technologies AG

发明人： Julien Lebon ,  Yiqun Cao ,  Ulrich Glaser

IPC分类号： G01R31/00

CPC分类号： G01R31/2841 ,  G01R31/002

摘要： An apparatus and a method for generating signals for ESD stress testing an electronic device are disclosed. In an embodiment the apparatus is configured to receive a source signal including a source pulse, delay the source pulse to generate a test signal including a test pulse with a pulse width in an ESD time range and generate an auxiliary signal including an auxiliary pulse with a pulse width in the ESD time range.

摘要翻译： 公开了一种用于产生电子装置的ESD应力测试信号的装置和方法。 在一个实施例中，该装置被配置为接收包括源脉冲的源信号，延迟源脉冲以产生包括具有ESD时间范围内的脉冲宽度的测试脉冲的测试信号，并产生包括辅助脉冲的辅助信号， 脉冲宽度在ESD时间范围内。

公开(公告)号：US09413166B2

公开(公告)日：2016-08-09

申请号：US14162410

申请日：2014-01-23

申请人： Infineon Technologies AG

发明人： Andreas Rupp ,  Yiqun Cao ,  Ulrich Glaser

IPC分类号： H02H9/04

CPC分类号： H02H9/04

摘要： A circuit is described comprising electrostatic discharge (ESD) protection circuitry, keep-off circuitry and ESD detection circuitry. When the ESD detection circuitry detects an ESD event, the ESD detection circuitry is configured to both enable the ESD protection circuitry and disable the keep-off circuitry.

摘要翻译： 描述了包括静电放电（ESD）保护电路，保护断路电路和ESD检测电路的电路。 当ESD检测电路检测到ESD事件时，ESD检测电路被配置为启用ESD保护电路并禁用保护电路。

公开(公告)号：US20150207313A1

公开(公告)日：2015-07-23

申请号：US14162410

申请日：2014-01-23

申请人： Infineon Technologies AG

发明人： Andreas Rupp ,  Yiqun Cao ,  Ulrich Glaser

IPC分类号： H02H9/04

CPC分类号： H02H9/04

摘要： A circuit is described comprising electrostatic discharge (ESD) protection circuitry, keep-off circuitry and ESD detection circuitry. When the ESD detection circuitry detects an ESD event, the ESD detection circuitry is configured to both enable the ESD protection circuitry and disable the keep-off circuitry.

摘要翻译： 描述了包括静电放电（ESD）保护电路，保护断路电路和ESD检测电路的电路。 当ESD检测电路检测到ESD事件时，ESD检测电路被配置为启用ESD保护电路并禁用保护电路。

公开(公告)号：US09899367B2

公开(公告)日：2018-02-20

申请号：US15153276

申请日：2016-05-12

申请人： Infineon Technologies AG

发明人： Kai Esmark ,  Yiqun Cao ,  Donald Dibra

IPC分类号： H01L29/66 ,  H01L27/02 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L27/0255 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7816

摘要： An embodiment of an integrated circuit includes a minimum lateral dimension of a semiconductor well at a first surface of a semiconductor body. The integrated circuit further includes a first lateral DMOSFET having a load path electrically coupled to a load pin. The first lateral DMOSFET is configured to control a load current through a load element electrically coupled to the load pin. A minimum lateral dimension of a drain region of the first lateral DMOSFET at the first surface of the semiconductor body is more than 50% greater than the minimum lateral dimension.