公开(公告)号：US20030186502A1

公开(公告)日：2003-10-02

申请号：US10249997

申请日：2003-05-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  INFINEON TECHNOLOGIES NORTH AMERICA CORP.

发明人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

IPC分类号： H01L021/8242 ,  H01L021/76

CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

摘要翻译： 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

公开(公告)号：US20040150056A1

公开(公告)日：2004-08-05

申请号：US10355726

申请日：2003-01-31

申请人： Infineon Technologies North America Corp ,  International Business Machines Corporation

发明人： Haining Yang ,  Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Rajeev Malik ,  Hongwen Yan ,  Ravikumar Ramachandran

IPC分类号： H01L029/76 ,  H01L029/94

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/76838

摘要： A method of fabricating a semiconductor device having a dielectric structure on which a gate stack having a gate stack surface is formed, the gate stack having one or more gate metal layers comprising a gate metal, wherein the gate metal is recessed from the gate stack surface by a chemical etch, is provided. The method includes oxidizing the gate metal of the gate stack selectively to form a smooth side wall on the gate stack, and depositing a gate spacer to the gate stack.

摘要翻译： 一种制造具有电介质结构的半导体器件的方法，其上形成具有栅叠层表面的栅极叠层，所述栅叠层具有一个或多个包含栅极金属的栅极金属层，其中栅极金属从栅叠层表面凹陷 通过化学蚀刻。 所述方法包括选择性地氧化栅极堆叠的栅极金属，以在栅极堆叠上形成平滑的侧壁，以及将栅极间隔物沉积到栅极叠层。

公开(公告)号：US20040131979A1

公开(公告)日：2004-07-08

申请号：US10338273

申请日：2003-01-07

申请人： International Business Machines Corporation ,  Infineon Technologies North America Corp.

发明人： Wai-kin Li ,  Rajeev Malik ,  Joseph J. Mezzapelle

IPC分类号： G03C005/00

CPC分类号： G03F7/091 ,  G03F7/11 ,  Y10S430/151

摘要： A process for prohibiting amino group transport from the top surface of a layered semiconductor wafer to a photoresist layer introduces a thin film oxynitride over the silicon nitride layer using a high temperature step of nitrous oxide (N2O) plus oxygen (O2) at approximately 300null C. for about 50 to 120 seconds. By oxidizing the silicon nitride layer, the roughness resulting from the adverse affects of amino group transport eliminated. Moreover, this high temperature step, non-plasma process can be used with the more advanced 193 nanometer technology, and is not limited to the 248 nanometer technology. A second method for exposing the silicon nitride layer to an oxidizing ambient, prior to the application of antireflective coating, introduces a mixture of N2H2 and oxygen (O2) ash at a temperature greater than or equal to 250null C. for approximately six minutes. This is followed by an O2 plasma clean and/or an Ozone clean, and then the subsequent layering of the ARC and photoresist.

摘要翻译： 用于禁止从层状半导体晶片的顶表面到光致抗蚀剂层的氨基转移的方法使用氧化亚氮（N 2 O）和氧（O 2）在约300°的高温步骤在氮化硅层上引入薄膜氧氮化物 C.约50至120秒。 通过氧化氮化硅层，消除了由氨基转移的不利影响产生的粗糙度。 此外，这种高温步骤，非等离子体工艺可以采用更先进的193纳米技术，并不限于248纳米技术。 在施加抗反射涂层之前将氮化硅层暴露于氧化环境的第二种方法是在大于或等于250℃的温度下引入N 2 H 2和氧（O 2）灰分的混合物约6分钟。 之后是O2等离子体清洁和/或臭氧清洁，然后再分层ARC和光刻胶。

公开(公告)号：US20040102001A1

公开(公告)日：2004-05-27

申请号：US10305063

申请日：2002-11-27

申请人： Infineon Technologies North America Corp.

发明人： Thomas Goebel ,  Werner Robl ,  Rajeev Malik ,  Mihel Seitz

IPC分类号： H01R013/60 ,  H01L021/8242 ,  H01R013/66 ,  H01L021/44

CPC分类号： H01L27/10888 ,  H01L21/76882

摘要： In a process for preparing contact layer (CL) contacts for DRAM products filled with aluminum by physical vapor deposition (PVD), the improvements of increasing the process window of wafers per hour per deposition chamber and filling the contact hole without a void to obtain high aspect ratio CL contacts, comprising: a) introducing a semiconductor wafer into a deposition chamber, the semiconductor comprising a bottom layer of an intermetal dielectric, a target layer intermetal dielectric patterned to form a trench that includes contact holes or vias and/or conductive line openings disposed on the bottom inter metal dielectric, the target layer further including a target conductor or metal layer, the target conductor or metal layer is a substrate having diffusion regions therein or conductive lines formed thereon; b) cold depositing a first Al layer unchucked on the bottom and sidewalls of the via and on top of the target layer using high sputter power and low temperatures due to absence of heating the wafer; c) hot depositing a thin second Al layer on the first Al layer at a temperature greater than about 300null C. to cause reflow of the second Al layer on a hot chuck to provide improved sidewall coverage and a thin continuous seed layer for a subsequent third layer Al deposition; and d) after the reflow in step c) hot depositing slowly a third Al layer on the second Al layer at a temperature greater than about 300null C. to cause reflow of the third Al layer on the hot chuck to fill the contact hole with a void.

摘要翻译： 在通过物理气相沉积（PVD）制备填充有铝的DRAM产品的接触层（CL）接触的过程中，改进了每个沉积室每小时增加晶片的工艺窗口并填充接触孔而没有空隙以获得高 宽高比CL触点，包括：a）将半导体晶片引入沉积室，所述半导体包括金属间电介质的底层，图案化以形成包括接触孔或通孔和/或导线的沟槽的目标层金属间电介质 开口设置在底部金属间电介质上，目标层还包括目标导体或金属层，目标导体或金属层是其中具有扩散区域的基板或其上形成的导电线; b）由于不加热所述晶片而使用高溅射功率和低温冷沉积在所述通孔的底部和侧壁上以及所述目标层的顶部上的第一Al层; c）在大于约300℃的温度下在第一Al层上热沉积薄的第二Al层，以在热卡盘上引起第二Al层的回流以提供改进的侧壁覆盖和用于随后的薄的连续种子层 第三层Al沉积; 和d）在步骤c）中的回流之后，在大于约300℃的温度下缓慢地在第二Al层上沉积第三Al层，以使热卡盘上的第三Al层回流填充接触孔 一个空白