公开(公告)号：US06687233B1

公开(公告)日：2004-02-03

申请号：US09343647

申请日：1999-06-29

申请人： Albert Chen ,  Ingolf Held

发明人： Albert Chen ,  Ingolf Held

IPC分类号： H04L1226

CPC分类号： H04L1/0046 ,  H04L1/0054 ,  H04L1/0067 ,  H04L1/08

摘要： A method of rate detection at a receiving end of a code division multiple access (CDMA) system, in which system the effective data rate is variably selected at the transmitting end from an applicable rate set including a full rate and lower rates, each lower rate being the full rate divided by a different integer, and encoded symbols are repeated for the lower rates to maintain a constant apparent symbol transmission rate, includes the formation of scaled correlations between data entering a Viterbi decoder, after any required de-repetition, and re-encoded data at each of the possible data rates in the applicable rate set. Rate decision logic sequentially considers the full and lower candidate data rates in descending order, choosing the considered candidate data rate to be the actual data rate if certain conditions are met. A first of the conditions is whether the scaled correlation for the considered data rate plus a predetermined biasing threshold associated therewith is greater than or equal to the largest of the scaled correlations for the other data rates, and a second condition depends on whether CRC checking if available for the considered data rate. If CRC checking is available for the considered data rate, the second condition is satisfied if CRC checking has not failed. If CRC checking is not available, it is determined as the second condition whether the scaled correlation for the considered data rate is equal to or greater than a further predetermined threshold associated therewith.

摘要翻译： 一种在码分多址（CDMA）系统的接收端进行速率检测的方法，其中系统在发送端从包括全速率和较低速率的适用速率集可变地选择有效数据速率，每个较低速率 以全速率除以不同的整数，并且对于较低速率重复编码符号以保持恒定的视在符号传输速率，包括在任何所需的重复之后进入维特比解码器的数据之间的缩放相关性的形成，并且re 在适用的速率集中的每个可能的数据速率的编码数据。 速率决策逻辑按顺序考虑全部和较低的候选数据速率，如果满足某些条件，则将所考虑的候选数据速率选择为实际数据速率。 第一个条件是所考虑的数据速率的缩放相关性加上与其相关联的预定偏置阈值是否大于或等于其他数据速率的缩放相关的最大值，第二个条件取决于CRC校验是否 可用于考虑的数据速率。 如果CRC检查可用于所考虑的数据速率，则如果CRC校验没有失败，则满足第二条件。 如果CRC校验不可用，则确定所考虑的数据速率的缩放相关性是否等于或大于与其相关联的另一预定阈值的第二条件。

公开(公告)号：US06463097B1

公开(公告)日：2002-10-08

申请号：US09343648

申请日：1999-06-29

申请人： Ingolf Held ,  Albert Chen

发明人： Ingolf Held ,  Albert Chen

IPC分类号： H04B346

CPC分类号： H04L1/08 ,  H04L1/0046 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/0068

摘要： A method of rate detection at a receiving end of a code division multiple access (CDMA) system, in which system the effective data rate is variably selected at the transmitting end from an applicable rate set including a full rate and lower rates, each lower rate being the full rate divided by a different integer, and encoded symbols are repeated for the lower rates to maintain a constant apparent bit or symbol transmission rate. The data rate is first determined by a coarse decision method employing symbol repetition characteristics before any Viterbi decoding of the data, the data is de-punctured and de-repeated where required, and first Viterbi decoded at the first determined data rate, and data available from or after the first Viterbi decoding is evaluated to determine whether to select the data rate as equal to the first determined data rate.

摘要翻译： 一种在码分多址（CDMA）系统的接收端进行速率检测的方法，其中系统在发送端从包括全速率和较低速率的适用速率集可变地选择有效数据速率，每个较低的速率 以全速率除以不同的整数，对于较低的速率重复编码的符号以保持恒定的视差或符号传输速率。 数据速率首先由在数据的任意维特比解码之前采用符号重复特征的粗略决策方法来确定，数据在需要时进行去穿孔和去重复，并且以第一确定的数据速率进行第一维特比解码，并且可获得数据 从第一维特比解码之后或之后进行评估，以确定是否选择数据速率等于第一确定的数据速率。

公开(公告)号：US20120120310A1

公开(公告)日：2012-05-17

申请号：US13357339

申请日：2012-01-24

申请人： Paulus W. F. Gruijters ,  Marcus M.G. Quax ,  Ingolf Held

发明人： Paulus W. F. Gruijters ,  Marcus M.G. Quax ,  Ingolf Held

IPC分类号： H04N7/01

CPC分类号： G06F9/30032 ,  G06F9/30029 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3455

摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

摘要翻译： 可编程信号处理电路用于（去）交织数据流。 来自信号流的数据被存储在数据存储器（28）中，并以不同的顺序读取。 可编程信号处理电路用于计算用于所述存储和/或读取的地址。 可编程信号处理电路具有指令集，其包含用于计算已经用于所述存储和/或读取的先前地址的地址的指令。 响应于指令，可编程信号处理电路将来自旧地址操作数的多个位的位置和新地址结果的位的形式作为来自旧地址操作数的位组合的逻辑功能。 通过重复执行包含用于计算地址的地址更新指令的程序循环来形成连续地址。

公开(公告)号：US08433881B2

公开(公告)日：2013-04-30

申请号：US13357339

申请日：2012-01-24

申请人： Paulus W. F. Gruijters ,  Marcus M. G. Quax ,  Ingolf Held

发明人： Paulus W. F. Gruijters ,  Marcus M. G. Quax ,  Ingolf Held

IPC分类号： G06F9/355

CPC分类号： G06F9/30032 ,  G06F9/30029 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3455

摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

摘要翻译： 可编程信号处理电路用于（去）交织数据流。 来自信号流的数据被存储在数据存储器（28）中，并以不同的顺序读取。 可编程信号处理电路用于计算用于所述存储和/或读取的地址。 可编程信号处理电路具有指令集，其包含用于计算已经用于所述存储和/或读取的先前地址的地址的指令。 响应于指令，可编程信号处理电路将来自旧地址操作数的多个位的位置和新地址结果的位的形式作为来自旧地址操作数的位组合的逻辑功能。 通过重复执行包含用于计算地址的地址更新指令的程序循环来形成连续地址。

公开(公告)号：US20100017453A1

公开(公告)日：2010-01-21

申请号：US11721050

申请日：2005-12-13

申请人： Ingolf Held ,  Marcus M.G. Quax ,  Paulus W.F. Gruijters

发明人： Ingolf Held ,  Marcus M.G. Quax ,  Paulus W.F. Gruijters

IPC分类号： G06F9/302 ,  G06F17/10 ,  G06F9/312

CPC分类号： H04L25/067 ,  G06F9/30007 ,  H04L27/38

摘要： A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.

摘要翻译： 可编程信号处理电路具有指令处理电路（23,24.26），其具有包括解映射指令的指令集。 指令处理电路（23,24,26）具有操作数输入（30a），用于接收来自寄存器文件（22）的解映射指令的复数操作数和用于写入解映射的解映射结果的结果输出（34） 指令寄存器文件（22）。 指令处理电路（23,24,26）响应于解映射指令来确定至少四个比特量度，每个指标在复平面中指示复数相对于相应边界线的相对位置。 指令处理电路（23,24,26）在解映射结果中将至少四位比特度量的组合写入结果输出（34）。

公开(公告)号：US08108651B2

公开(公告)日：2012-01-31

申请号：US11721052

申请日：2005-12-13

申请人： Paulus W. F. Gruijters ,  Marcus M. G. Quax ,  Ingolf Held

发明人： Paulus W. F. Gruijters ,  Marcus M. G. Quax ,  Ingolf Held

IPC分类号： G06F12/06 ,  H04N7/12

CPC分类号： G06F9/30032 ,  G06F9/30029 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3455

摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

摘要翻译： 可编程信号处理电路用于（去）交织数据流。 来自信号流的数据被存储在数据存储器（28）中，并以不同的顺序读取。 可编程信号处理电路用于计算用于所述存储和/或读取的地址。 可编程信号处理电路具有指令集，其包含用于计算已经用于所述存储和/或读取的先前地址的地址的指令。 响应于指令，可编程信号处理电路将来自旧地址操作数的多个位的位置和新地址结果的位的形式作为来自旧地址操作数的位组合的逻辑功能。 通过重复执行包含用于计算地址的地址更新指令的程序循环来形成连续地址。

公开(公告)号：US09184953B2

公开(公告)日：2015-11-10

申请号：US11721050

申请日：2005-12-13

申请人： Ingolf Held ,  Marcus M. G. Quax ,  Paulus W. F. Gruijters

发明人： Ingolf Held ,  Marcus M. G. Quax ,  Paulus W. F. Gruijters

IPC分类号： G06F9/30 ,  H04L27/38 ,  H04L25/06

CPC分类号： H04L25/067 ,  G06F9/30007 ,  H04L27/38

摘要： A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.

摘要翻译： 可编程信号处理电路具有指令处理电路（23,24.26），其具有包括解映射指令的指令集。 指令处理电路（23,24,26）具有操作数输入（30a），用于接收来自寄存器文件（22）的解映射指令的复数操作数和用于写入解映射的解映射结果的结果输出（34） 指令寄存器文件（22）。 指令处理电路（23,24,26）响应于解映射指令来确定至少四个比特量度，每个指标在复平面中指示复数相对于相应边界线的相对位置。 指令处理电路（23,24,26）在解映射结果中将至少四位比特度量的组合写入结果输出（34）。

公开(公告)号：US20100039567A1

公开(公告)日：2010-02-18

申请号：US11721052

申请日：2005-12-13

申请人： Paulus W.F. Gruijters ,  Marcus M.G. Quax ,  Ingolf Held

发明人： Paulus W.F. Gruijters ,  Marcus M.G. Quax ,  Ingolf Held

IPC分类号： H04N9/64

CPC分类号： G06F9/30032 ,  G06F9/30029 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3455

摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

摘要翻译： 可编程信号处理电路用于（去）交织数据流。 来自信号流的数据被存储在数据存储器（28）中，并以不同的顺序读取。 可编程信号处理电路用于计算用于所述存储和/或读取的地址。 可编程信号处理电路具有指令集，其包含用于计算已经用于所述存储和/或读取的先前地址的地址的指令。 响应于指令，可编程信号处理电路将来自旧地址操作数的多个位的位置和新地址结果的位的形式作为来自旧地址操作数的位组合的逻辑功能。 通过重复执行包含用于计算地址的地址更新指令的程序循环来形成连续地址。

公开(公告)号：US07058399B2

公开(公告)日：2006-06-06

申请号：US09901571

申请日：2001-07-11

申请人： Oliver Klein ,  Ingolf Held

发明人： Oliver Klein ,  Ingolf Held

IPC分类号： H04Q7/20 ,  H04B1/60 ,  H04B17/00 ,  H04B17/02

CPC分类号： H04B1/7113 ,  H04B1/7117 ,  H04B2001/70706

摘要： The present invention provides a search window delay tracking procedure for use in a multipath search processor of a CDMA radio receiver. A channel impulse response is estimated for a received signal containing plural paths, each path having a corresponding path delay. A search window defines a delay profile that contains the plural paths of the received signal. A mean or average delay is calculated for the estimated channel impulse response (CIR), and an error is determined between the mean CIR delay and a desired or target delay position of the Cir. search window. An adjustment is made to reduce that error to align the targeted position of the search window and the mean CIR delay. A Doppler frequency is estimated for each path. The adjustment is made taking into account a Doppler effect caused by relative movement between the transmitter and receiver.

摘要翻译： 本发明提供了一种在CDMA无线电接收机的多路径搜索处理器中使用的搜索窗延迟跟踪程序。 对于包含多个路径的接收信号估计信道脉冲响应，每个路径具有对应的路径延迟。 搜索窗口定义包含接收信号的多个路径的延迟分布。 对于估计的信道脉冲响应（CIR）计算平均或平均延迟，并且在平均CIR延迟和Cir的期望或目标延迟位置之间确定误差。 搜索窗口。 进行调整以减少该误差以使搜索窗口的目标位置与平均CIR延迟对齐。 估计每个路径的多普勒频率。 考虑到发射机和接收机之间的相对运动引起的多普勒效应进行调整。