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    Add compare select circuit and method implementing a viterbi algorithm
    4.
    发明授权
    Add compare select circuit and method implementing a viterbi algorithm 失效
    添加比较选择电路和实现维特比算法的方法

    公开(公告)号：US6148431A

    公开(公告)日：2000-11-14

    申请号：US49158

    申请日：1998-03-26

    申请人： Inkyu Lee ,  Jeffrey Lee Sonntag

    发明人： Inkyu Lee ,  Jeffrey Lee Sonntag

    IPC分类号： G06F11/10 ,  H03M13/23 ,  H03M13/41 ,  H03M13/03

    CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4115 ,  H03M13/413

    摘要： A detector system employing a Viterbi algorithm includes an apparatus and method which constructs a double-state trellis structure for determining a most likely received symbol sequence with respect to an observed sequence of channel output samples. In the double state trellis, pairs of states are identified having equivalent branch metric values which also have a same decision during a path select, thus allowing these pairs of states to share a compare operation of a previous state metric. Consequently, to calculate an updated or current state metric value, an add, compare and select (ACS) circuit may compare only the previous state metric values to determine a minimum value for a transition between two states while combining each previous state metric value with its corresponding branch metric to provide an updated or current state metric value.

    摘要翻译： 采用维特比算法的检测器系统包括一种装置和方法，该装置和方法构建用于相对于观察到的信道输出样本序列确定最可能的接收符号序列的双状态网格结构。 在双状态网格中，识别出具有等效分支度量值的状态对，其在路径选择期间也具有相同的决定，从而允许这些状态对共享先前状态度量的比较操作。 因此，为了计算更新或当前状态度量值，加法，比较和选择（ACS）电路可以仅比较先前的状态度量值以确定两个状态之间的转换的最小值，同时将每个先前的状态度量值与其 相应的分支度量以提供更新或当前状态度量值。

    APPARATUS AND METHOD FOR SPATIAL MULTIPLEXING IN MULTI INPUT MULTI OUTPUT SYSTEM
    8.
    发明申请
    APPARATUS AND METHOD FOR SPATIAL MULTIPLEXING IN MULTI INPUT MULTI OUTPUT SYSTEM 有权
    多输入多输出系统中空间多路复用的装置与方法

    公开(公告)号：US20090285324A1

    公开(公告)日：2009-11-19

    申请号：US12467765

    申请日：2009-05-18

    申请人： Inkyu Lee ,  Sung-Hyun Moon ,  Chae-Man Lim

    发明人： Inkyu Lee ,  Sung-Hyun Moon ,  Chae-Man Lim

    IPC分类号： H04B7/02 ,  H04J11/00

    CPC分类号： H04B7/0417

    摘要： Methods and apparatus for spatial multiplexing in a closed-loop Multi Input Multi Output (MIMO) system are provided. In a method of operating a receiver in an MIMO system, a signal transmitted by a transmitter is received. Blockwise-Orthogonalized Spatial Multiplexing (B-OSM) is performed on the received signal. Feedback information determined by performing the B-OSM on the received signal is fed back to the transmitter.

    摘要翻译： 提供了一种闭环多输入多输出（MIMO）系统中空间复用的方法和装置。 在MIMO系统中操作接收机的方法中，接收由发射机发送的信号。 对接收到的信号执行块向正交空间复用（B-OSM）。 通过对接收到的信号执行B-OSM确定的反馈信息被反馈给发送器。

    Block processing in a maximum a posteriori processor for reduced power consumption
    9.
    发明授权
    Block processing in a maximum a posteriori processor for reduced power consumption 失效
    在最大后验处理器中进行块处理，以降低功耗

    公开(公告)号：US07353450B2

    公开(公告)日：2008-04-01

    申请号：US10054687

    申请日：2002-01-22

    申请人： Thaddeus J. Gabara ,  Inkyu Lee ,  Marissa L. Lopez-Vallejo ,  Syed Mujtaba

    发明人： Thaddeus J. Gabara ,  Inkyu Lee ,  Marissa L. Lopez-Vallejo ,  Syed Mujtaba

    IPC分类号： H03M13/03

    CPC分类号： H04L1/0055 ,  H03M13/3905 ,  H03M13/395 ,  H03M13/3972 ,  H04L1/0053

    摘要： A maximum a posteriori (MAP) processor employs a block processing technique for the MAP algorithm to provide a parallel architecture that allows for multiple word memory read/write processing and voltage scaling of a given circuit implementation. The block processing technique forms a merged trellis with states having modified branch inputs to provide the parallel structure. When block processing occurs, the trellis may be modified to show transitions from the oldest state at time k−N to the present state at time k. For the merged trellis, the number of states remains the same, but each state receives 2N input transitions instead of the two input transitions. Branch metrics associated with the transitions in the merged trellis are cumulative, and are employed for the update process of forward and backward probabilities by the MAP algorithm. During the update process, the read/write operation for an implementation transfers N words of length N for each update operation, but the frequency (and hence, number) of update operations is reduced by a factor of N. Such voltage scaling and multiple word memory read/write may provide reduced power consumption for a given implementation of MAP processor in, for example, a DSP.

    摘要翻译： 最大后验（MAP）处理器采用用于MAP算法的块处理技术来提供允许给定电路实现的多个字存储器读/写处理和电压缩放的并行架构。 块处理技术形成具有修改的分支输入的状态的合并网格以提供并行结构。 当块处理发生时，网格可以被修改以显示从时间k-N处的最旧状态到时间k的当前状态的转换。 对于合并的网格，状态数量保持不变，但是每个状态都接收两个输入转换，而不是两个输入转换。 与合并网格中的转换相关联的分支度量是累积的，并且被MAP算法用于前向和后向概率的更新过程。 在更新过程中，对于每个更新操作，实现的读/写操作传送N个长度为N的字，但更新操作的频率（因此，数量）减少了N倍。这种电压缩放和多个字 存储器读/写可以为例如DSP中的MAP处理器的给定实现提供降低的功耗。

    Method and apparatus for extracting reliability information from partial response channels
    10.
    发明授权
    Method and apparatus for extracting reliability information from partial response channels 有权
    从部分响应信道中提取可靠性信息的方法和装置

    公开(公告)号：US06587987B1

    公开(公告)日：2003-07-01

    申请号：US09611887

    申请日：2000-07-07

    申请人： Bane V. Vasic ,  Inkyu Lee ,  Jeffrey L. Sonntag

    发明人： Bane V. Vasic ,  Inkyu Lee ,  Jeffrey L. Sonntag

    IPC分类号： H03M1300

    CPC分类号： H03M13/47

    摘要： The present invention is a method and system for generating soft outputs by taking advantage of the fact that, in PR channels, there exists a set of error event sequences that occurs more often than others. This results in a soft output extractor with significantly lower complexity than the prior art SOVA system. Minimum distance error event sequences are identified and soft information or bit reliabilities are extracted from the PR channel based on the identified sequences. The soft information is then used by an iterative error control decoder correct errors more efficiently.

    摘要翻译： 本发明是一种通过利用以下事实来生成软输出的方法和系统：在PR信道中存在比其他的更频繁出现的一组错误事件序列。 这导致软输出提取器具有比现有技术的SOVA系统低得多的复杂度。 识别最小距离误差事件序列，并且基于所识别的序列从PR信道提取软信息或比特可靠性。 然后，软信息由迭代误差控制解码器更有效地校正错误。