公开(公告)号：US10203577B2

公开(公告)日：2019-02-12

申请号：US15434070

申请日：2017-02-16

Applicant: Innolux Corporation

Inventor： Te-Yi Chen ,  Han-Tsung Su ,  Hsin-Hung Lin ,  Ker-Yih Kao

IPC: H01L29/45 ,  H01L29/66 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/786

Abstract: An active element array substrate including a substrate, a first metal layer, a first insulation layer, a semiconductor layer, a first patterned conductive layer, a second metal layer, a second insulation layer, and a second patterned conductive layer is provided. The semiconductor layer is disposed on the first insulation layer. The first patterned conductive layer is disposed on the first insulation layer and covers a partial region of the semiconductor layer. The second metal layer is disposed on the first patterned conductive layer. The second insulation layer is disposed on the second metal layer and covers at least a partial region of the second metal layer, the first patterned conductive layer, the semiconductor layer, and the first insulation layer. The second patterned conductive layer is disposed on the second insulation layer and overlapped with the first patterned conductive layer. A display panel is also provided.

公开(公告)号：US20170235172A1

公开(公告)日：2017-08-17

申请号：US15434070

申请日：2017-02-16

Applicant: Innolux Corporation

Inventor： Te-Yi Chen ,  Han-Tsung Su ,  Hsin-Hung Lin ,  Ker-Yih Kao

IPC: G02F1/1368 ,  H01L29/45 ,  H01L29/417 ,  G02F1/1343 ,  G02F1/1362

CPC classification number: G02F1/1368 ,  G02F1/136286 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2001/136236 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/786

Abstract: An active element array substrate including a substrate, a first metal layer, a first insulation layer, a semiconductor layer, a first patterned conductive layer, a second metal layer, a second insulation layer, and a second patterned conductive layer is provided. The semiconductor layer is disposed on the first insulation layer. The first patterned conductive layer is disposed on the first insulation layer and covers a partial region of the semiconductor layer. The second metal layer is disposed on the first patterned conductive layer. The second insulation layer is disposed on the second metal layer and covers at least a partial region of the second metal layer, the first patterned conductive layer, the semiconductor layer, and the first insulation layer. The second patterned conductive layer is disposed on the second insulation layer and overlapped with the first patterned conductive layer. A display panel is also provided.