公开(公告)号：US09665289B1

公开(公告)日：2017-05-30

申请号：US14959141

申请日：2015-12-04

Applicant: Inphi Corporation

Inventor： Dat Tuan Mach ,  Alejandro Lopez-Sosa ,  Chao Xu ,  Chien-Hsin Lee

IPC: G09F3/06 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F11/27

CPC classification number: G06F3/061 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/067 ,  G06F11/27 ,  G06F13/1668 ,  G06F13/4068

Abstract: Techniques are described for processing signal information from a high speed communication bus. The techniques include determining spatial regions on an eye by sampling a plurality of time and voltage points to determine a two-dimensional matrix. Then, the points are assigned a numerical value from combined time and voltage functions based upon a distance from eye edges (e.g., minimum setup time requirement and minimum hold time requirement along the time dimension). Sampling to generate the matrix may comprise selecting an initial point, splitting a first margin along a first dimension into equally spaced regions, and then sampling a second margin along a second dimension into equally spaced regions. Determining the points is based on shifting a strobe signal (DQS) position and a data signal (DQ) position and running a plurality of memory built-in self test (BIST) engines and a plurality of results of BIST tests.

公开(公告)号：US09099165B1

公开(公告)日：2015-08-04

申请号：US13791792

申请日：2013-03-08

Applicant: Inphi Corporation

Inventor： Chien-Hsin Lee

IPC: G11C29/04 ,  G11C8/06 ,  G11C16/08

CPC classification number: G11C8/06 ,  G11C29/848

Abstract: A memory device comprising an interface device and a plurality of memory arrays. The interface device includes an address match table comprising at least a revised address corresponding to a spare memory location and a control module configured to determine address information from the address stream from an address command bus coupled to the host controller during a run time operation. The control module is configured to compare each address from the address stream and determine whether each address matches with a stored address in the address match table to identify a bad address and configured to replace the bad address with the revised address of the spare memory location. The device also has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The memory device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells being addressable using the address match table.

Abstract translation: 一种存储器件，包括接口器件和多个存储器阵列。 所述接口装置包括地址匹配表，所述地址匹配表至少包括与备用存储器位置对应的修改地址，以及控制模块，被配置为在运行时操作期间从耦合到所述主机控制器的地址命令总线从所述地址流确定地址信息。 控制模块被配置为比较来自地址流的每个地址，并且确定每个地址是否与地址匹配表中的存储地址相匹配，以识别不良地址，并将其配置为用备用存储器位置的修改地址替换坏地址。 该设备还具有多个存储器阵列。 每个存储器阵列包括多个存储单元。 存储器件具有包括多个备用存储器单元的存储器单元的备用组。 多个备用存储单元中的每一个可使用地址匹配表进行寻址。

公开(公告)号：US09230620B1

公开(公告)日：2016-01-05

申请号：US13783155

申请日：2013-03-01

Applicant: Inphi Corporation

Inventor： Chien-Hsin Lee

IPC: G06F13/00 ,  G11C7/10 ,  G06F12/00

CPC classification number: G11C7/1072 ,  G11C5/04 ,  G11C7/10 ,  G11C11/4076 ,  G11C29/76 ,  G11C29/783 ,  G11C29/785

Abstract: A memory interface for a plurality of DRAM devices comprising an input DRAM address matching module includes a local memory comprising a plurality of data entries, wherein the plurality of data entries comprising a plurality of DRAM addresses and a plurality of associated pointers, and wherein the plurality of associated pointers comprise output DRAM addresses, and a matching mechanism coupled to the local memory, wherein the matching mechanism is configured to receive the input DRAM address, wherein the matching mechanism is configured to determine whether the input DRAM address is specified in the plurality of data entries, and when the input DRAM address is specified in the plurality of data entries, the matching mechanism is configured to output an associated pointer associated with the input DRAM address.

Abstract translation: 用于包括输入DRAM地址匹配模块的多个DRAM器件的存储器接口包括包括多个数据条目的本地存储器，其中所述多个数据条目包括多个DRAM地址和多个相关联的指针，并且其中所述多个 相关联的指针包括输出DRAM地址以及耦合到本地存储器的匹配机制，其中所述匹配机制被配置为接收所述输入DRAM地址，其中所述匹配机制被配置为确定所述输入DRAM地址是否在所述多个 数据条目，并且当在多个数据条目中指定输入DRAM地址时，匹配机制被配置为输出与输入DRAM地址相关联的关联指针。

公开(公告)号：US09239355B1

公开(公告)日：2016-01-19

申请号：US13786325

申请日：2013-03-05

Applicant: Inphi Corporation

Inventor： Andrew Burstein ,  Larry Kan ,  Chien-Hsin Lee ,  Srinivas Bamdhamravuri ,  David Wang

IPC: G06F19/00 ,  G01R31/26 ,  G06F17/00

CPC classification number: G11C29/16 ,  G11C5/04 ,  G11C11/401

Abstract: An interface device for a memory module comprising a plurality of DRAMs includes a memory configured to store DRAM test program instructions, and a programmable processing device coupled to the memory, wherein the programmable processing device is configured to receive input data and input memory addresses from an external processor, wherein the programmable processing device is configured to provide data and memory addresses to the plurality of DRAMs, and wherein the programmable processing device is programmed to perform operations specified by the DRAM test program instructions.

Abstract translation: 包括多个DRAM的存储器模块的接口装置包括被配置为存储DRAM测试程序指令的存储器和耦合到存储器的可编程处理设备，其中可编程处理设备被配置为从一个或多个存储器地址接收输入数据和输入存储器地址 外部处理器，其中所述可编程处理设备被配置为向所述多个DRAM提供数据和存储器地址，并且其中所述可编程处理设备被编程为执行由所述DRAM测试程序指令指定的操作。