Vertical error correction code for DRAM memory
    1.
    发明授权
    Vertical error correction code for DRAM memory 有权
    DRAM存储器的垂直纠错码

    公开(公告)号:US08996960B1

    公开(公告)日:2015-03-31

    申请号:US13797583

    申请日:2013-03-12

    CPC classification number: H03M13/17 G06F11/1048

    Abstract: Techniques for operating a DIMM apparatus. The apparatus comprises a plurality of DRAM devices numbered from 0 through N−1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N−1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of DRAM devices.

    Abstract translation: 操作DIMM装置的技术。 该装置包括从0到N-1编号的多个DRAM器件,其中N是大于7(7)的整数,每个DRAM器件被配置在衬底模块中; 包括从0到N-1编号的多个数据缓冲器(DB)的缓冲器集成电路器件,其中N是大于7(7)的整数,每个数据缓冲器对应于一个DRAM器件; 以及与多个DRAM设备相关联的多个纠错模块(“ECM”)。

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