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公开(公告)号：US09846669B2
公开(公告)日：2017-12-19
申请号：US15223412
申请日：2016-07-29
Applicant: INPHI CORPORATION
Inventor： Sreenivas Krishnan , Nirmal Raj Saxena
CPC classification number: G06F13/4022 , G06F13/4027 , G06F13/4282 , H04B10/27 , H04J14/0267 , H04L12/64 , H04L12/66 , H04L49/15 , H04Q11/0005 , H04Q2011/009 , Y02D10/14 , Y02D10/151
Abstract: A computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and can include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. The plurality of rack modules can each include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.
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公开(公告)号：US10572425B2
公开(公告)日：2020-02-25
申请号：US16267748
申请日：2019-02-05
Applicant: INPHI CORPORATION
Inventor： Sreenivas Krishnan , Nirmal Raj Saxena
Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.
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公开(公告)号：US09250831B1
公开(公告)日：2016-02-02
申请号：US14194574
申请日：2014-02-28
Applicant: INPHI CORPORATION
Inventor： Nirmal Raj Saxena , Sreenivas Krishnan , David Wang
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0613 , G06F3/0635 , G06F3/0644 , G06F3/0658 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F12/0813 , G06F13/4022 , Y02D10/14 , Y02D10/151
Abstract: Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.
Abstract translation: 大规模并行和以内存为中心的计算系统的技术。 该系统具有通过一个或多个通信信道彼此可操作地耦合的多个处理单元。 多个处理单元中的每一个具有ISMn接口装置。 多个ISMn接口设备中的每一个耦合到连接到每个处理单元的ISMe端点。 该系统具有以分解体系结构配置的多个DRAM或闪存，以及可操作地以分解结构耦合多个DRAM或闪速存储器的一个或多个交换节点。 该系统具有多个高速光缆，其配置为以100G或更大的传输速率进行通信，以便于从多个处理单元中的任何一个到多个DRAM或闪存中的任何一个的通信。
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Patent Agency Ranking
公开(公告)号：US08996960B1
公开(公告)日：2015-03-31
申请号：US13797583
申请日：2013-03-12
Applicant: Inphi Corporation
Inventor： Nirmal Raj Saxena , David Wang , Hamid Rategh , Lawrence Tse
CPC classification number: H03M13/17 , G06F11/1048
Abstract: Techniques for operating a DIMM apparatus. The apparatus comprises a plurality of DRAM devices numbered from 0 through N−1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N−1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of DRAM devices.
Abstract translation: 操作DIMM装置的技术。 该装置包括从0到N-1编号的多个DRAM器件，其中N是大于7（7）的整数，每个DRAM器件被配置在衬底模块中; 包括从0到N-1编号的多个数据缓冲器（DB）的缓冲器集成电路器件，其中N是大于7（7）的整数，每个数据缓冲器对应于一个DRAM器件; 以及与多个DRAM设备相关联的多个纠错模块（“ECM”）。
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公开(公告)号：US10235318B2
公开(公告)日：2019-03-19
申请号：US15812493
申请日：2017-11-14
Applicant: INPHI CORPORATION
Inventor： Sreenivas Krishnan , Nirmal Raj Saxena
Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.
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公开(公告)号：US10929325B2
公开(公告)日：2021-02-23
申请号：US16738984
申请日：2020-01-09
Applicant: INPHI CORPORATION
Inventor： Sreenivas Krishnan , Nirmal Raj Saxena
Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.
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公开(公告)号：US09430437B1
公开(公告)日：2016-08-30
申请号：US13963329
申请日：2013-08-09
Applicant: Inphi Corporation
Inventor： Sreenivas Krishnan , Nirmal Raj Saxena
CPC classification number: G06F13/4022 , G06F13/4027 , G06F13/4282 , H04B10/27 , H04J14/0267 , H04L12/64 , H04L12/66 , H04L49/15 , H04Q11/0005 , H04Q2011/009 , Y02D10/14 , Y02D10/151
Abstract: A computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and can include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. The plurality of rack modules can each include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.
Abstract translation: 配置有分解输入/输出的计算机网络系统。 该系统可以被配置在叶脊结构中，并且可以包括耦合到网络源的路由器，耦合到路由器的多个核心交换机，耦合到多个核心交换机中的每一个的多个聚合器交换机，以及多个 耦合到所述多个聚合器开关中的每一个的机架模块。 多个机架模块可以各自包括具有下游聚合器模块的I / O设备，每个具有PCIe接口的多个服务器设备和聚集每个PCIe接口的上游聚合器模块。 可以通过多个串行通道的聚合在下游和上游聚合器模块之间配置高速链路，以提供长距离可靠的高速比特流传输，这样可以更好地利用资源和独立于服务器数量的内存容量的可扩展性 。
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公开(公告)号：US09348539B1
公开(公告)日：2016-05-24
申请号：US14194416
申请日：2014-02-28
Applicant: INPHI CORPORATION
Inventor： Nirmal Raj Saxena , David Wang , Christopher Haywood , Eric McDonald , Chao Xu
IPC: G06F3/06
CPC classification number: G11C11/005 , G11C5/04
Abstract: A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.
Abstract translation: 混合存储器系统。 该系统可以包括耦合到耦合到多个DRAM和多个闪存模块的混合存储器缓冲器（HMB）的处理器。 HMB模块可以包括由SerDes（串行器/解串器）接口耦合的存储器存储控制器（MSC）模块和近端存储器处理（NMP）模块。 该系统可以利用混合（混合存储器型）存储器系统架构，其适用于在用于工业标准计算机系统的相同存储器子系统中支持低延迟DRAM设备和低成本NAND闪存器件。
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