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    Hitless re-arrangements in coupled digital phase-locked loops
    1.
    发明授权
    Hitless re-arrangements in coupled digital phase-locked loops 有权

    公开(公告)号：US10666269B2

    公开(公告)日：2020-05-26

    申请号：US16451433

    申请日：2019-06-25

    Applicant: Integrated Device Technology, Inc.

    Inventor： Menno Spijker

    IPC: H03B5/04 ,  H03L7/07 ,  H03L7/099 ,  H04W88/08 ,  H03L7/08 ,  H03L7/093 ,  H03B5/32

    Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.

    HITLESS RE-ARRANGEMENTS IN COUPLED DIGITAL PHASE-LOCKED LOOPS
    2.
    发明申请
    HITLESS RE-ARRANGEMENTS IN COUPLED DIGITAL PHASE-LOCKED LOOPS 审中-公开

    公开(公告)号：US20190312580A1

    公开(公告)日：2019-10-10

    申请号：US16451433

    申请日：2019-06-25

    Applicant: Integrated Device Technology, Inc.

    Inventor： Menno Spijker

    IPC: H03L7/08 ,  H03L7/093 ,  H03B5/32 ,  H03L7/07 ,  H03B5/04 ,  H03L7/099

    Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.

    HITLESS RE-ARRANGEMENTS IN COUPLED DIGITAL PHASE-LOCKED LOOPS
    4.
    发明申请
    HITLESS RE-ARRANGEMENTS IN COUPLED DIGITAL PHASE-LOCKED LOOPS 审中-公开

    公开(公告)号：US20180159542A1

    公开(公告)日：2018-06-07

    申请号：US15833117

    申请日：2017-12-06

    Applicant: Integrated Device Technology, Inc.

    Inventor： Menno Spijker

    IPC: H03L7/08 ,  H03L7/093 ,  H03B5/32 ,  H03B5/04

    CPC classification number: H03L7/08 ,  H03B5/04 ,  H03B5/32 ,  H03L7/07 ,  H03L7/093 ,  H03L7/0991 ,  H04W88/08

    Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.

    Hitless re-arrangements in coupled digital phase-locked loops
    6.
    发明授权
    Hitless re-arrangements in coupled digital phase-locked loops 有权

    公开(公告)号：US10355699B2

    公开(公告)日：2019-07-16

    申请号：US15833117

    申请日：2017-12-06

    Applicant: Integrated Device Technology, Inc.

    Inventor： Menno Spijker

    IPC: H03L7/07 ,  H03L7/08 ,  H03L7/093 ,  H03L7/099 ,  H03B5/04 ,  H03B5/32 ,  H04W88/08

    Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.

    Dual-coupled phase-locked loops for clock and packet-based synchronization
    8.
    发明授权
    Dual-coupled phase-locked loops for clock and packet-based synchronization 有权
    用于时钟和基于分组的同步的双耦合锁相环

    公开(公告)号：US09369270B1

    公开(公告)日：2016-06-14

    申请号：US14212598

    申请日：2014-03-14

    Applicant: Integrated Device Technology, Inc.

    Inventor： Menno Spijker

    IPC: H03D3/24 ,  H04L7/033 ,  H03L7/07

    CPC classification number: H04L7/0331 ,  H03L7/07 ,  H04J3/0641 ,  H04J3/0658 ,  H04J3/0667

    Abstract: A Synchronous Ethernet (SyncE) network device includes a pair of phase-locked loops including a first phase-locked loop responsive to a SyncE input clock and a second phase-locked loop coupled to the first phase-locked loop. The second phase-locked loop is configured to be simultaneously lockable to both the SyncE input clock via the first phase-locked loop and an IEEE 1588 packet stream, during a locked mode of operation, and also lockable to the SyncE input clock during a holdover mode of operation which is triggered in response to a failure of the IEEE 1588 packet stream.

    Abstract translation: 同步以太网（SyncE）网络设备包括一对锁相环，包括响应于SyncE输入时钟的第一锁相环和耦合到第一锁相环的第二锁相环。 第二锁相环被配置为在锁定操作模式期间通过第一锁相环和IEEE1588分组流同时锁定SyncE输入时钟，并且还可以在保持期间锁定到SyncE输入时钟 响应于IEEE 1588分组流的故障触发的操作模式。

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