公开(公告)号：US10075284B1

公开(公告)日：2018-09-11

申请号：US15364602

申请日：2016-11-30

Applicant: Integrated Device Technology, Inc.

Inventor： Silvana Rodrigues ,  Michael Rupert ,  Zaher Baidas ,  Leon Goldin

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/49 ,  H04L12/935

CPC classification number: H04L7/033 ,  H04J3/0688 ,  H04J3/0697 ,  H04L25/4902 ,  H04L49/30

Abstract: A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.

公开(公告)号：US09852039B1

公开(公告)日：2017-12-26

申请号：US15015094

申请日：2016-02-03

Applicant: Integrated Device Technology, Inc.

Inventor： Leon Goldin ,  Silvana Rodrigues

IPC: G06F11/00 ,  G06F11/26 ,  G06F11/22 ,  G06F11/273

CPC classification number: G06F11/261 ,  G06F11/2205

Abstract: An evaluation board and a method for evaluating Phase Locked Loop (PLL) timing devices. The evaluation board includes an input and output circuit disposed on a circuit board along with control logic, and a plurality of PLL-timed physical devices that are identical to the physical devices used in the customer's communication system. A first connector receptacle and a second connector receptacle are coupled to the control logic and to one or more of the PLL-timed physical devices, and are configured to receive a PLL card including a PLL timing device. A third connector receptacle is coupled in series between the first connector receptacle and the second connector receptacle and is configured to receive a backplane emulator card having electrical characteristics emulating a backplane of the customer's communication system.