公开(公告)号：US20170161075A1

公开(公告)日：2017-06-08

申请号：US15021442

申请日：2015-06-01

Applicant: Intel Corporation

Inventor： ALEXANDR TITOV ,  DMITRY M. MASLENNIKOV ,  SERGEY Y. SHISHLOV ,  SERGEY P. SCHERBININ ,  VALENTIN A. BUROV ,  RON GABOR ,  DENIS G. MOTIN ,  OLEG SHIMKO ,  KAMIL GARIFULLIN ,  ALEXANDER V. BUTUZOV ,  EVGENIY N. PODKORYTOV ,  ANDREY CHUDNOVETS

IPC: G06F9/38 ,  G06F9/44 ,  G03F7/00 ,  G06F9/30 ,  G03F1/36 ,  G03F1/70

CPC classification number: G06F9/38 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0005 ,  G06F8/445 ,  G06F9/30003 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3889 ,  G06F9/44

Abstract: In an embodiment, a processor includes a plurality of cores. Each core may include strand logic to, for each strand of a plurality of strands, fetch an instruction group uniquely associated with the strand, wherein the instruction group is one of a plurality of instruction groups, wherein the plurality of instruction groups is obtained by dividing instructions of an application program according to instruction criticality. The strand logic may also be to retire the instruction group in an original order of the application program. Other embodiments are described and claimed.