公开(公告)号：US20170161075A1

公开(公告)日：2017-06-08

申请号：US15021442

申请日：2015-06-01

Applicant: Intel Corporation

Inventor： ALEXANDR TITOV ,  DMITRY M. MASLENNIKOV ,  SERGEY Y. SHISHLOV ,  SERGEY P. SCHERBININ ,  VALENTIN A. BUROV ,  RON GABOR ,  DENIS G. MOTIN ,  OLEG SHIMKO ,  KAMIL GARIFULLIN ,  ALEXANDER V. BUTUZOV ,  EVGENIY N. PODKORYTOV ,  ANDREY CHUDNOVETS

IPC: G06F9/38 ,  G06F9/44 ,  G03F7/00 ,  G06F9/30 ,  G03F1/36 ,  G03F1/70

CPC classification number: G06F9/38 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0005 ,  G06F8/445 ,  G06F9/30003 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3889 ,  G06F9/44

Abstract: In an embodiment, a processor includes a plurality of cores. Each core may include strand logic to, for each strand of a plurality of strands, fetch an instruction group uniquely associated with the strand, wherein the instruction group is one of a plurality of instruction groups, wherein the plurality of instruction groups is obtained by dividing instructions of an application program according to instruction criticality. The strand logic may also be to retire the instruction group in an original order of the application program. Other embodiments are described and claimed.

公开(公告)号：US20160328172A1

公开(公告)日：2016-11-10

申请号：US14706936

申请日：2015-05-07

Applicant: INTEL CORPORATION

Inventor： LIHU RAPPOPORT ,  JARED W. STARK ,  KAMIL GARIFULLIN ,  FRANCK SALA ,  PAVEL I. KRYUKOV ,  STANISLAV SHWARTSMAN

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0631 ,  G06F3/06 ,  G06F3/0604 ,  G06F3/0671 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/384 ,  G06F12/0802

Abstract: A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.

Abstract translation: 描述了使用虚拟寄存器进行有效的存储器重命名预测的方法和装置。 例如，设备的一个实施例包括：存储器执行单元（MEU），用于执行存储和加载操作，以分别将存储数据存储到存储器中并从存储器加载数据; 分配给存储和加载操作的多个存储器重命名（MRN）寄存器，每个MRN寄存器存储与存储操作相关联的数据，使得数据可用于后续加载操作; 以及至少一个MRN预测器，其包括用于向每个MRN寄存器分配虚拟存储器重命名（VMRN）寄存器的数据结构，MRN预测器，使用标识MRN的值来响应于负载和/或存储操作来查询数据结构 分配给负载和/或存储操作的寄存器，以确定与负载和/或存储操作相关联的当前VMRN寄存器。