公开(公告)号：US20150134896A1

公开(公告)日：2015-05-14

申请号：US14536805

申请日：2014-11-10

Applicant: Intel Corporation

Inventor： ALI-REZA ADL-TABATABAI ,  YANG NI ,  BRATIN SAHA ,  VADIM BASSIN ,  GAD SHEAFFER ,  DAVID CALLAHAN ,  JAN GRAY

IPC: G06F12/08 ,  G06F9/46

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/621

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在第一线程中执行事务性存储器（TM）事务的方法，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块，并且获取所述块上的写监视器 在第一缓冲器中的块的位置处的数据被更新的遇到时间获得块的所有权。 描述和要求保护其他实施例。

公开(公告)号：US20160216973A9

公开(公告)日：2016-07-28

申请号：US13956495

申请日：2013-08-01

Applicant: Intel Corporation

Inventor： Koichi Yamada ,  GAD SHEAFFER ,  JAN GRAY ,  LANDY WANG ,  MARTIN TAILLEFER ,  ARUN KISHAN ,  ALI-REZA ADL-TABATABAI ,  DAVID CALLAHAN

IPC: G06F9/38

CPC classification number: G06F9/467 ,  G06F9/30076 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.