公开(公告)号：US20230401109A1

公开(公告)日：2023-12-14

申请号：US18237860

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Niall D. MCDONNELL ,  Ambalavanar ARULAMBALAM ,  Te Khac MA ,  Surekha PERI ,  Pravin PATHAK ,  James CLEE ,  An YAN ,  Steven POLLOCK ,  Bruce RICHARDSON ,  Vijaya Bhaskar KOMMINENI ,  Abhinandan GUJJAR

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5038

Abstract: Examples described herein relate to a load balancer that is configured to selectively perform ordering of requests from the one or more cores, allocate the requests into queue elements prior to allocation to one or more receiver cores of the one or more cores to process the requests, and perform two or more operations of: adjust a number of queues associated with a core of the one or more cores by changing a number of consumer queues (CQs) allocated to a single domain, adjust a number of target cores in a group of target cores to be load balanced, and order memory space writes from multiple caching agents (CAs).

公开(公告)号：US20240118739A1

公开(公告)日：2024-04-11

申请号：US18542452

申请日：2023-12-15

Applicant: Intel Corporation

Inventor： Abhinandan GUJJAR ,  Ashok Kumar KALADI

IPC: G06F1/329 ,  G06F1/3296 ,  G06F11/34

CPC classification number: G06F1/329 ,  G06F1/3296 ,  G06F11/3409

Abstract: Methods, apparatus, and computer programs are disclosed for managing processor power consumption based on message queue utilization. In one embodiment, a method comprising: distributing messages to a set of processor cores of a processor, wherein one message is distributed per distribution round to one queue within a set of queues, each queue corresponding to one processor core within the set of processor cores and including one or more queue entries to be processed by the one processor core, and where the distribution is based on utilization of the set of queues; based on utilization of a corresponding queue for a processor core of the set of processor cores, determining a power state for the processor core to be changed to; and distributing a message to the corresponding queue, the message to cause the processor core to be set to the power state.