公开(公告)号：US20220416503A1

公开(公告)日：2022-12-29

申请号：US17357938

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Priyanka DOBRIYAL ,  Aditi MALLIK ,  Saeed FATHOLOLOUMI ,  Ankur AGRAWAL ,  Anna PRAKASH ,  Hemant Mahesh SHAH ,  Raiyomand ASPANDIAR ,  Neil Raymund CARANTO

IPC: H01S5/024 ,  H01S5/34

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to thermal routing techniques within a hybrid silicon laser or photonics integrated circuit to facilitate heat extraction during laser operation. In particular dual metal layers, with a top metal layer thermally coupled with P node above a quantum well and extending substantially under a heat sink, and a bottom metal layer thermally coupled with an N node, where the top metal layer and the bottom metal layer are not electrically coupled. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199486A1

公开(公告)日：2022-06-23

申请号：US17131642

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Aditi MALLIK ,  Chen ZHUANG ,  Raghuram NARAYAN

IPC: H01L23/367 ,  H01L23/373

Abstract: A semiconductor package comprises a substrate and a ceramic carrier mounted to the substrate. An integrated circuit (IC) die is mounted to the ceramic carrier. A heat extraction path away from the IC die comprises: i) a thermal interface material over the IC die, the thermal interface material having a thickness of approximately 25 to 80 um; ii) an integrated heat spreader over the thermal interface material; iii) a ceramic carrier plate over the integrated heat spreader; and iv) an electrically conductive thermal pad between the ceramic carrier plate and a housing of the semiconductor package.

公开(公告)号：US20240069287A1

公开(公告)日：2024-02-29

申请号：US18271791

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Vinod ADIVARAHAN ,  Liqiang CUI ,  Aditi MALLIK ,  Boping XIE ,  Sunil PRIYADARSHI

IPC: G02B6/36

CPC classification number: G02B6/3636

Abstract: A fiber array unit (200) and a photonics system (890), a fiber array unit (200) comprises a substrate (205) with a first el end and a second end. A first mesa (207) is adjacent to the first end and a second mesa (209) is adjacent to the second end. A v-groove (211) is in the first mesa (207) and a slot (213) is in the second mesa (209). The v-groove (211) is aligned with the slot (213).

公开(公告)号：US20210210478A1

公开(公告)日：2021-07-08

申请号：US17191615

申请日：2021-03-03

Applicant: Intel Corporation

Inventor： Susheel JADHAV ,  Juan DOMINGUEZ ,  Ankur AGRAWAL ,  Kenneth BROWN ,  Yi LI ,  Jing CHEN ,  Aditi MALLIK ,  Xiaoyu HONG ,  Thomas LILJEBERG ,  Andrew C. ALDUINO ,  Ling LIAO ,  David HUI ,  Ren-Kang CHIOU ,  Harinadh POTLURI ,  Hari MAHALINGAM ,  Lobna KAMYAB ,  Sasanka KANUPARTHI ,  Sushrutha Reddy GUJJULA ,  Saeed FATHOLOLOUMI ,  Priyanka DOBRIYAL ,  Boping XIE ,  Abiola AWUJOOLA ,  Vladimir TAMARKIN ,  Keith MEASE ,  Stephen KEELE ,  David SCHWEITZER ,  Brent ROTHERMEL ,  Ning TANG ,  Suresh POTHUKUCHI ,  Srikant NEKKANTY ,  Zhichao ZHANG ,  Kaiyuan ZENG ,  Baikuan WANG ,  Donald TRAN ,  Ravindranath MAHAJAN ,  Baris BICEN ,  Grant SMITH

IPC: H01L25/18 ,  H01L23/473 ,  H01R12/71

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonic engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonic engines are communicatively coupled to the die through the first package substrate and the second package substrate.