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    SUBSTRATE CAVITY WITH ALIGNMENT FEATURES TO ALIGN AN OPTICAL CONNECTOR
    1.
    发明申请
    SUBSTRATE CAVITY WITH ALIGNMENT FEATURES TO ALIGN AN OPTICAL CONNECTOR 有权

    公开(公告)号：US20220413240A1

    公开(公告)日：2022-12-29

    申请号：US17357941

    申请日：2021-06-24

    Applicant: Intel Corporation

    Inventor： Srikant NEKKANTY ,  Pooya TADAYON ,  Wesley MORGAN ,  Tarek A. IBRAHIM ,  Sai VADLAMANI

    IPC: G02B6/42

    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a cavity created in a package substrate, where the surface of the substrate at the bottom of the cavity, or alignment features at the surface of the substrate at the bottom of the cavity are used to accurately align a lens of a FAU to a lens of a PIC. In embodiments, the surface of the substrate at the bottom of the cavity has additional standoff pedestal features to aid in height tolerance control of the FAU to properly align the FAU lens when attached. Other embodiments may be described and/or claimed.

    DIFFERENTIAL CROSSTALK SELF-CANCELATION IN STACKABLE STRUCTURES
    2.
    发明申请
    DIFFERENTIAL CROSSTALK SELF-CANCELATION IN STACKABLE STRUCTURES 有权

    公开(公告)号：US20210272892A1

    公开(公告)日：2021-09-02

    申请号：US16804516

    申请日：2020-02-28

    Applicant: Intel Corporation

    Inventor： Zhichao ZHANG ,  Zhe CHEN ,  Srikant NEKKANTY ,  Sriram SRINIVASAN

    IPC: H01L23/498 ,  H01L23/58

    Abstract: Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.

    MICRO SOCKET ELECTRICAL COUPLINGS FOR DIES
    4.
    发明申请
    MICRO SOCKET ELECTRICAL COUPLINGS FOR DIES 有权

    公开(公告)号：US20220200183A1

    公开(公告)日：2022-06-23

    申请号：US17132921

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Srikant NEKKANTY ,  Debendra MALLIK ,  Joe F. WALCZYK ,  Saikumar JAYARAMAN ,  Feroz MOHAMMAD

    IPC: H01R13/11 ,  H01R12/58 ,  H01L25/075 ,  H01L23/00 ,  H01L23/532

    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.

    ACTIVE OPTICAL COUPLER
    5.
    发明申请
    ACTIVE OPTICAL COUPLER 有权

    公开(公告)号：US20220196942A1

    公开(公告)日：2022-06-23

    申请号：US17132955

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Divya PRATAP ,  Srikant NEKKANTY

    IPC: G02B6/42

    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical couplers that provide optical coupling at or proximate to an edge of a silicon photonics package, to allow the package to optically couple with other devices or peripherals. In embodiments, the active optical coupler is optically coupled with a photonics IC (PIC) inside the photonics package, and provides an optical coupling mechanism for optical pathways outside the photonics package. The active optical coupler may include electrical circuitry and may be coupled to the package substrate to provide data related to the operation of the active optical coupler. Other embodiments may be described and/or claimed.

    ELECTRICAL CONNECTOR WITH INSULATED CONDUCTIVE LAYER
    8.
    发明申请
    ELECTRICAL CONNECTOR WITH INSULATED CONDUCTIVE LAYER 有权

    公开(公告)号：US20210305196A1

    公开(公告)日：2021-09-30

    申请号：US16828651

    申请日：2020-03-24

    Applicant: Intel Corporation

    Inventor： Morten JENSEN ,  Michael RYAN ,  Srikant NEKKANTY ,  Joe F. WALCZYK

    IPC: H01L23/00 ,  H01R13/24 ,  H01R12/71

    Abstract: An interconnect that has an electrically conductive layer, where a first and second insulator layers are coupled with the conductive layer. A region of the conductive layer includes an opening of a portion of the first insulator layer the second insulator layer that are adjacent to the region. An electrical connector of a first device is electrically coupled to a portion of the region on a first side of the conductive layer and an electrical conductor of a second device is electrically coupled with a portion of the region on the second side. Also, an interconnect coupled with a substrate that includes a cylinder extending from a side of the substrate with a plate coupled at the end of the cylinder with an opening that includes two or more tabs of the plate extending into the opening to receive a connector.

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