公开(公告)号：US20240332166A1

公开(公告)日：2024-10-03

申请号：US18129873

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Seda CEKLI ,  Sudipto NASKAR ,  Ananya DUTTA ,  Supanee SUKRITTANON ,  Akshit PEER ,  Navneethakrishnan SALIVATI ,  Jeffery BIELEFELD ,  Makram ABD EL QADER ,  Mauro J. KOBRINSKY ,  Sachin VAIDYA

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295

Abstract: Integrated circuit structures having air gaps are described. In an example, an integrated circuit structure includes alternating conductive lines and air gaps above a first dielectric layer. A dielectric structure is between adjacent ones of the conductive lines and over the air gaps. A first etch stop layer is on the dielectric structure but not on the conductive lines. A second etch stop layer is on the first etch stop layer and on the conductive lines. A second dielectric layer is above the second etch stop layer. A conductive via structure is in the second dielectric layer, in the second etch stop layer, and on one of the conductive lines.

公开(公告)号：US20230369221A1

公开(公告)日：2023-11-16

申请号：US17743899

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Clifford J. ENGEL ,  Richard H. LIVENGOOD ,  Mauro J. KOBRINSKY ,  Robert L. BRISTOL ,  Akshit PEER

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L21/76898

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.

公开(公告)号：US20230369207A1

公开(公告)日：2023-11-16

申请号：US17743948

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Clifford J. ENGEL ,  Robert L. BRISTOL ,  Richard H. LIVENGOOD ,  Mahesh TANNIRU ,  Akshit PEER ,  Mauro J. KOBRINSKY ,  Kevin Lai LIN

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76877

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a first conductive line and a second conductive line in a first dielectric layer, the second conductive line laterally spaced apart from the first conductive line. The integrated circuit structure also includes a first conductive via and a second conductive via in a second dielectric layer, the second dielectric layer over the first dielectric layer, the second conductive via laterally spaced apart from the first conductive via, the first conductive via vertically over and connected to the first conductive line, and the second conductive via vertically over but separated from the second conductive line.