公开(公告)号：US20220093505A1

公开(公告)日：2022-03-24

申请号：US17031825

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Christopher J. JEZEWSKI ,  Kevin Lai LIN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Via connections for staggered interconnect lines are disclosed. An interconnect structure includes a first plurality of interconnects and a second plurality of interconnects, wherein the first plurality of interconnects and the second plurality of interconnects are staggered such that individual interconnects of the second plurality of interconnects are laterally offset from individual interconnects of the first plurality of interconnects. The interconnect structure also includes a via coupling an individual interconnect of the first plurality of interconnects to an individual interconnect of the second plurality of interconnects.

公开(公告)号：US20230369207A1

公开(公告)日：2023-11-16

申请号：US17743948

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Clifford J. ENGEL ,  Robert L. BRISTOL ,  Richard H. LIVENGOOD ,  Mahesh TANNIRU ,  Akshit PEER ,  Mauro J. KOBRINSKY ,  Kevin Lai LIN

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76877

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a first conductive line and a second conductive line in a first dielectric layer, the second conductive line laterally spaced apart from the first conductive line. The integrated circuit structure also includes a first conductive via and a second conductive via in a second dielectric layer, the second dielectric layer over the first dielectric layer, the second conductive via laterally spaced apart from the first conductive via, the first conductive via vertically over and connected to the first conductive line, and the second conductive via vertically over but separated from the second conductive line.

公开(公告)号：US20210043567A1

公开(公告)日：2021-02-11

申请号：US16534104

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Mark ANDERS ,  Himanshu KAUL ,  Ram KRISHNAMURTHY ,  Kevin Lai LIN ,  Mauro KOBRINSKY

IPC: H01L23/528 ,  G06F17/50 ,  G11C5/06

Abstract: Embodiments disclosed herein include a semiconductor device with interconnects with non-uniform heights. In an embodiment, the semiconductor device comprises a semiconductor substrate, and a back end of line (BEOL) stack over the semiconductor substrate. In an embodiment, the BEOL stack comprises first interconnects and second interconnects in an interconnect layer of the BEOL stack. In an embodiment, the first interconnects have a first height and the second interconnects have a second height that is different than the first height.

公开(公告)号：US20230369211A1

公开(公告)日：2023-11-16

申请号：US17743954

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Clifford J. ENGEL ,  Robert L. BRISTOL ,  Richard H. LIVENGOOD ,  Ilan RONEN ,  Kevin Lai LIN

IPC: H01L23/528

CPC classification number: H01L23/5283

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a plurality of conductive structures along corresponding ones of a plurality of line tracks along a first direction. The integrated circuit structure also includes a white space track included within the plurality of line tracks, the white space track having a width along a second direction greater than a width of an individual one of the plurality of line tracks, the second direction orthogonal to the first direction. A conductive structure is along the white space track.

公开(公告)号：US20230369206A1

公开(公告)日：2023-11-16

申请号：US17743913

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Kevin Lai LIN ,  Clifford J. ENGEL

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76877

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a plurality of conductive lines in a dielectric layer, individual ones of the plurality of conductive lines along a direction and spaced at a same interval. A conductive structure is in the dielectric layer, the conductive structure laterally between but not in contact with a pair of the plurality of conductive lines.

公开(公告)号：US20220199516A1

公开(公告)日：2022-06-23

申请号：US17129852

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Ramanan V. CHEBIAM ,  Colin T. CARVER ,  Kevin Lai LIN ,  Mauro KOBRINSKY

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines above a substrate, individual ones of the conductive interconnect lines having a top and sidewalls. An etch stop layer is on the top and along an entirety of the sidewalls of the individual ones of the conductive interconnect lines.

公开(公告)号：US20210043500A1

公开(公告)日：2021-02-11

申请号：US16534063

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Kevin Lai LIN ,  Mauro KOBRINSKY ,  Mark ANDERS ,  Himanshu KAUL ,  Ram KRISHNAMURTHY

IPC: H01L21/768 ,  H01L23/528

Abstract: Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.