公开(公告)号：US20190287813A1

公开(公告)日：2019-09-19

申请号：US16435240

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert Lindsey BRISTOL ,  Alan M. MYERS

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L21/033

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

公开(公告)号：US20220157619A1

公开(公告)日：2022-05-19

申请号：US17592442

申请日：2022-02-03

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert Lindsey BRISTOL ,  Alan M. MYERS

IPC: H01L21/3213 ,  H01L21/768 ,  H01L21/033 ,  H01L23/522

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

公开(公告)号：US20180158694A1

公开(公告)日：2018-06-07

申请号：US15575283

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert Lindsey BRISTOL ,  Alan M. MYERS

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2224/16225

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

公开(公告)号：US20170250104A1

公开(公告)日：2017-08-31

申请号：US15523330

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Kanwal Jit SINGH ,  Alan M. MYERS

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/764 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L29/78 ,  H01L2224/16225

Abstract: A method including forming a sacrificial material between metal lines of an integrated circuit structure; forming a mask on the sacrificial material; and after forming the mask, removing the sacrificial material to leave a void between the metal lines. An apparatus including an integrated circuit substrate; a first metallization level on the substrate; a second metallization;and a mask disposed between the first metallization level and the second metallization level, the mask including a dielectric material having a porosity select to allow mass transport therethrough, wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.