公开(公告)号：US20220413591A1

公开(公告)日：2022-12-29

申请号：US17358224

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Pritesh P. SHAH ,  Suresh CHEMUDUPATI ,  Alexander GENDLER ,  David HUNT ,  Christopher M. MACNAMARA ,  Ofer NATHAN ,  Adwait PURANDARE ,  Ankush VARMA

IPC: G06F1/3287 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/50

Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

公开(公告)号：US20240085973A1

公开(公告)日：2024-03-14

申请号：US18514807

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Praveen MOSALIKANTI ,  Nasser A. KURD ,  Alexander GENDLER

IPC: G06F1/3296 ,  G01R19/25 ,  H03K5/24 ,  H03K19/20 ,  H03L7/093 ,  H03L7/095

CPC classification number: G06F1/3296 ,  G01R19/2513 ,  H03K5/24 ,  H03K19/20 ,  H03L7/093 ,  H03L7/095

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

公开(公告)号：US20210181831A1

公开(公告)日：2021-06-17

申请号：US17181832

申请日：2021-02-22

Applicant: Intel Corporation

Inventor： Praveen MOSALIKANTI ,  Nasser A. KURD ,  Alexander GENDLER

IPC: G06F1/3296 ,  H03L7/093 ,  G01R19/25 ,  H03L7/095 ,  H03K5/24 ,  H03K19/20

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

公开(公告)号：US20200272220A1

公开(公告)日：2020-08-27

申请号：US16285051

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Praveen MOSALIKANTI ,  Nasser KURD ,  Alexander GENDLER

IPC: G06F1/3296 ,  H03L7/093 ,  H03K19/20 ,  H03L7/095 ,  H03K5/24 ,  G01R19/25

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.