公开(公告)号：US20200320031A1

公开(公告)日：2020-10-08

申请号：US16779377

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173 ,  G06F1/10

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US10552357B2

公开(公告)日：2020-02-04

申请号：US15821492

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173 ,  G06F1/10

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US10073808B2

公开(公告)日：2018-09-11

申请号：US15039452

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173

CPC classification number: G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US20170083475A1

公开(公告)日：2017-03-23

申请号：US15039452

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/42 ,  G06F15/173 ,  G06F13/12

CPC classification number: G06F13/4282 ,  G06F13/124 ,  G06F13/4273 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US11003610B2

公开(公告)日：2021-05-11

申请号：US16779377

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobel Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173 ,  G06F1/10

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US20180300275A1

公开(公告)日：2018-10-18

申请号：US15821492

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/40 ,  G06F1/10

CPC classification number: G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.