DYNAMIC MULTILEVEL MEMORY SYSTEM
    1.
    发明申请

    公开(公告)号:US20220229575A1

    公开(公告)日:2022-07-21

    申请号:US17710796

    申请日:2022-03-31

    Abstract: A system can dynamically migrate memory pages from near memory to far memory during runtime. A system basic input output system (BIOS) can program a first memory address space of size P and a second memory address space of size P to a near memory (NM) space of size (N) and a far memory (FM) space of size (M), where P equals N+M. For the first memory address space, the OS can manage the NM space and the FM space as a flat memory space with an address space of size P available. For the second memory address space, the OS can manage the NM space as a NM cache for FM, with an address space of size M available.

    VIRTUAL MACHINE REPLICATION AND MIGRATION
    2.
    发明申请

    公开(公告)号:US20200042343A1

    公开(公告)日:2020-02-06

    申请号:US16586859

    申请日:2019-09-27

    Abstract: Examples herein relate to checkpoint replication and copying of updated checkpoint data. For example, a memory controller coupled to a memory can receive a write request with an associated address to write or update checkpoint data and track updates to checkpoint data based on at least two levels of memory region sizes. A first level is associated with a larger memory region size than a memory region size associated with the second level. In some examples, the first level is a cache-line memory region size and the second level is a page memory region size. Updates to the checkpoint data can be tracked at the second level unless an update was previously tracked at the first level. Reduced amounts of updated checkpoint data can be transmitted during a checkpoint replication by using multiple region size trackers.

    TECHNIQUES TO EXPAND SYSTEM MEMORY VIA USE OF AVAILABLE DEVICE MEMORY

    公开(公告)号:US20220114086A1

    公开(公告)日:2022-04-14

    申请号:US17560007

    申请日:2021-12-22

    Abstract: Examples include techniques to expand system memory via use of available device memory. Circuitry at a device coupled to a host device partitions a portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload. The partitioned portion of memory capacity is reported to the host device as being available for use as a portion of system memory. An indication from the host device is received if the portion of memory capacity has been identified for use as a first portion of pooled system memory. The circuitry to monitor usage of the memory capacity used by the compute circuitry to execute the workload to decide whether to place a request to the host device to reclaim the memory capacity from the first portion of pooled system memory.

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