公开(公告)号：US20220114086A1

公开(公告)日：2022-04-14

申请号：US17560007

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Chace A. CLARK ,  James A. BOYD ,  Chet R. DOUGLAS ,  Andrew M. RUDOFF ,  Dan J. WILLIAMS

IPC: G06F12/02

Abstract: Examples include techniques to expand system memory via use of available device memory. Circuitry at a device coupled to a host device partitions a portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload. The partitioned portion of memory capacity is reported to the host device as being available for use as a portion of system memory. An indication from the host device is received if the portion of memory capacity has been identified for use as a first portion of pooled system memory. The circuitry to monitor usage of the memory capacity used by the compute circuitry to execute the workload to decide whether to place a request to the host device to reclaim the memory capacity from the first portion of pooled system memory.

公开(公告)号：US20180089099A1

公开(公告)日：2018-03-29

申请号：US15280965

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Ashok RAJ ,  Sivakumar RADHAKRISHNAN ,  Dan J. WILLIAMS ,  Vishal VERMA ,  Narayan RANGANATHAN ,  Chet R. DOUGLAS

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/65

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.