公开(公告)号：US10002654B2

公开(公告)日：2018-06-19

申请号：US14752464

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Jaydeep P Kulkarni ,  Pramod Kolar ,  Ankit Sharma ,  Subho Chatterjee ,  Karthik Subramanian ,  Farhana Sheikh ,  Wei-Hsiang Ma

IPC: G11C8/08 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419

Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.

公开(公告)号：US10713333B2

公开(公告)日：2020-07-14

申请号：US15777249

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ankit Sharma ,  Jaydeep Kulkarni

IPC: G06F17/14 ,  H04L27/26

Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.