公开(公告)号：US20220091652A1

公开(公告)日：2022-03-24

申请号：US17128076

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Pascal Meinerzhagen ,  Suyoung Bang ,  Abdullah Afzal ,  Karthik Subramanian ,  Muhammad Khellah ,  Arvind Raman

IPC: G06F1/324 ,  H03K19/0175 ,  G06F1/12 ,  G06F1/08 ,  G06F1/3296

Abstract: Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).

公开(公告)号：US10002654B2

公开(公告)日：2018-06-19

申请号：US14752464

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Jaydeep P Kulkarni ,  Pramod Kolar ,  Ankit Sharma ,  Subho Chatterjee ,  Karthik Subramanian ,  Farhana Sheikh ,  Wei-Hsiang Ma

IPC: G11C8/08 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419

Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.

公开(公告)号：US12007826B2

公开(公告)日：2024-06-11

申请号：US17128076

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Pascal Meinerzhagen ,  Suyoung Bang ,  Abdullah Afzal ,  Karthik Subramanian ,  Muhammad Khellah ,  Arvind Raman

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  G06F1/324 ,  G06F1/3296 ,  H03K19/0175

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/12 ,  G06F1/3296 ,  H03K19/017509

Abstract: Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).

公开(公告)号：US11320888B2

公开(公告)日：2022-05-03

申请号：US16124071

申请日：2018-09-06

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Muhammad Khellah ,  Arvind Raman ,  Ashish Choubal ,  Karthik Subramanian ,  Abdullah Afzal ,  Feroze Merchant

IPC: G06F1/00 ,  G06F1/3234 ,  H02M3/157 ,  G06F1/324 ,  H02M1/00

Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.

公开(公告)号：US20200081512A1

公开(公告)日：2020-03-12

申请号：US16124071

申请日：2018-09-06

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Muhammad Khellah ,  Arvind Raman ,  Ashish Choubal ,  Karthik Subramanian ,  Abdullah Afzal ,  Feroze Merchant

IPC: G06F1/32 ,  H02M3/157

Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.