公开(公告)号：US10002654B2

公开(公告)日：2018-06-19

申请号：US14752464

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Jaydeep P Kulkarni ,  Pramod Kolar ,  Ankit Sharma ,  Subho Chatterjee ,  Karthik Subramanian ,  Farhana Sheikh ,  Wei-Hsiang Ma

IPC: G11C8/08 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419

Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.

公开(公告)号：US09627039B2

公开(公告)日：2017-04-18

申请号：US14830679

申请日：2015-08-19

Applicant: Intel Corporation

Inventor： Jaydeep P Kulkarni ,  Muhammad M Khellah ,  James W Tschanz ,  Bibiche M Geuskens ,  Vivek K De

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/22 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C7/227 ,  G11C11/412 ,  G11C11/413

Abstract: Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.