公开(公告)号：US20220180905A1

公开(公告)日：2022-06-09

申请号：US17114407

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Ashraf B. Islam ,  Jaydip Bharatkumar Patel ,  Yasir Mohsin Husain ,  Balaji Srinivasan ,  Nicolas L. Irizarry

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  G11C7/14 ,  G11C8/08

Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.

公开(公告)号：US20230307043A1

公开(公告)日：2023-09-28

申请号：US17703921

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Jonathan Y. Wang ,  Yasir Mohsin Husain ,  Ashraf B. Islam

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0038 ,  G11C13/0026 ,  G11C13/0028 ,  H01L27/2481 ,  G11C13/0004 ,  H01L45/1233

Abstract: Techniques for current biasing for memory cells are disclosed. In the illustrative embodiment, a source follower sets a voltage on a bitline of a memory cell. The current through the source follower is limited by a current mirror in series with the source follower. When additional current is required that the source follower cannot supply, a feedback transistor is activated to provide additional current. Additionally, in some embodiments, the current through the feedback transistor is copied to a current mirror, and the copied current is used to sense the state of the memory cell.

公开(公告)号：US11139026B2

公开(公告)日：2021-10-05

申请号：US16782321

申请日：2020-02-05

Applicant: Intel Corporation

Inventor： Ashraf B. Islam

IPC: G11C13/00 ,  G06F3/06

Abstract: A variable reference based sensing scheme is described. In one example, performance of a memory command to access a crosspoint memory device such as a memory read or memory write command involves a sensing operation. In one example, a memory read operation involves applying a voltage across the memory cell and sensing current through the cell. The current through the memory cell is compared with one of multiple reference currents to determine the state of the memory cell. The reference current is selected based on the voltage applied across the memory for the sensing operation. Different reference currents may be used for different types of operations. For example, different reference currents may be selected for a write sensing operation than for a read sensing operation.

公开(公告)号：US12062410B2

公开(公告)日：2024-08-13

申请号：US17114407

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Ashraf B. Islam ,  Jaydip Bharatkumar Patel ,  Yasir Mohsin Husain ,  Balaji Srinivasan ,  Nicolas L. Irizarry

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.

公开(公告)号：US11139027B1

公开(公告)日：2021-10-05

申请号：US16946530

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Ashraf B. Islam ,  Kevin E. Arendt

IPC: G11C7/02 ,  G11C13/00

Abstract: A method, apparatus and system. The method includes: generating, during a read operation of a memory cell, a mirror current iMir1 at one of a WL node or a BL node of the memory cell opposite, respectively, one of a BL side or a WL side of the memory cell to which a current mode sense circuitry is connected, the iMir1 to reduce a value of the read voltage from VDM1 to VDM2, wherein the read voltage is between the WL node and the BL node; and sensing, using the current mode sense circuitry, a logic state of the memory cell at VDM2.